not followed for low jitter circuit for CNV signal

Hi,

We will contact the product owner and get back to you.

Thanks,
Janine

Hi Janine, 

    Thank you, 

I am waiting. 

Regards

Mohsin

Hi, 

 Any update on my query please? 

thank you 

Hi Mohsin,

The possible effect to observe due to excessive jitter in the CNV signal is degradation of SNR in the digitized signal. That is, a noisier measurement.

Given that you have an already manufactured board, I would suggest you just go ahead and test it as planned. If measurement performance issues arise, then all possible contributing factors should be studied, including jitter.

It is possible that jitter will not have a meaningful impact on your particular design; jitter is more of a concern with increasing SNR target and increasing signal frequency. On the SNR side, the system target in this case will not be better that the datasheet quoted 77.2dB of this 12-bit ADC. On the frequency side, it will depend on the signal being digitized, but it will be below ~2.2MHz. Generally speaking, this does not fall into the most challenging conditions with respect to jitter requirements, and an FPGA clock might be OK. One could try to do a broad assessment if jitter might be a concern if you could get an estimate of your CNV signal jitter and check that against a set of curves of theoretical SNR limit due to jitter vs signal frequency, such as that in figure 4 in this article that discusses jitter: https://www.analog.com/media/en/training-seminars/tutorials/MT-007.pdf

If CNV jitter were found to be a problem, the most straightforward way to reduce it is to change the source of of the CNV signal for one that is intrinsically less jittery, and interface it to the converter and FPGA through the circuit shown in page 30 in the datasheet.

Best regards,
Emilio

Hi Emilio,

      Thanks a lot, This is really helpfull.

Best Regards

Mohsin