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AD4001 SPI Configuration

Category: Datasheet/Specs
Product Number: AD4001

I am confused by the SPI options with the AD4001 and am hoping someone can give me feedback on the options.

Is it safe to connect 2x AD4001's in "CS MODE, 4-WIRE WITHOUT BUSY INDICATOR" along with an AD5674 on the same SPI bus?

The datasheet is pretty complicated, with the state of SDI, SCK, and CONV at different times determining the function of the communication.

I see that it suggests using CS MODE, 4-WIRE WITHOUT BUSY INDICATOR for the case of multiple AD4001 devices. I see it also has a daisy chain mode, and that the two options use different "chip select" lines.

What does SDO actually do in these modes?

If SDO on the AD4001 is actually active high or low while I am trying to talk to the AD5674 it would be bad, and I am struggling to figure out if my concern is valid.

In "CS MODE, 4-WIRE WITHOUT BUSY INDICATOR" mode, I think it says that it can share a bus, but I would love some clarity on how to avoid ending up with SDO going active high (or active low) due to activity on SCK. If it goes active high or active low just from SCK activity it would of course disrupt all hope of talking to another device.

I would also like to be able to test the high-Z mode, but that requires writing to the configuration register. I think that would require using daisy-chain mode rather than "CS MODE, 4-WIRE WITHOUT BUSY INDICATOR" because SDI needs to be sending data, but that implies to me that SDO will definitely always be going active high or active low when SCK is active -- how does that work? Is it hopeless to use a daisy-chain mode with other devices on the SPI bus?

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  • Hi,  .

    We'll look into this and get back to you.

    Regards,
    Jo

  • Dear Jo,

    Is there any hope of getting a clarification on this in the next few days? I need to make a choice whether to use this family of parts or find one that I am more confident that the communication will work for.

    This part looks excellent and I have already designed a front-end specifically for it, but I cannot risk making a PCB and finding after the fact that it cannot share a SPI bus.

    I will have to decide by tomorrow, it's unfortunately been 2 weeks and I have to move this project forward. This is the only thing left holding me up, whether I can have this AD4001 (or any other parts in this pin-compatible family) on the same SPI bus as my AD5674 DAC.

    Thanks!

  •  ,

    I think the best way to understand how the SPI is used in "CS MODE, 4-WIRE WITHOUT BUSY INDICATOR" is to have a look to the timing diagram provided in the datasheet.

    As you can see in this mode the SDO lines are in Hi-Z mode all the time except when they are transferring data. 

    In this case the SDI lines are used as Chip select and the must be high during the rise edge of CNV and also make sure that you bring high SDI line before the conversion time elapses. After this time, you can pull down SDI (CS) of the ADC you want to read data from.

    In this configuration if you want to read or write the registers then you need to pull down CNV and write the correct register access command:

    Regards

    Joan

  • Thank you for the clarification, it was not obvious to me that the straight flat lines were meant to indicate tristate.

    Could you please explain how to send and receive data from the second chip assumed to be attached?

    If I assume that SCK and SDI will have active digital data on them, can I just hold CNV high or low to prevent the chip from reading the SDI value as a CS signal?

    I see that you hold SDI high when you raise CNV, which makes me think I can just keep CNV low.

    The second example uses CNV as a CS line though, which makes holding it low sound bad. Based on the second diagram I feel like I need to hold CNV high in order to keep it from responding to SCK/SDI. Especially since SDI is also held high through the CNV edges in the second example, so the thing I see is CNV held high during communication in Example 1 but held low in Example 2 with the difference only being in how long.

    I wish this was more obvious to me, I am probably overthinking it. I see a dozen chips or more between you and TI that all have similar looking diagrams but they all confuse me for the same reason. Do you have any example circuits showing this device in a SPI bus with a second device that shows how to do it? I just did the obvious, but I have solder jumpers everywhere because I still don't trust this datasheet's information.

    I think I am totally failing to grasp the combinatoric logic used to configure the serial communication.

  • Hi ,

    Can I ask your schematic to understand what you are trying to do?

    But I think you are not going to be able to share the SDI, SDO and CLK lines with all three devices. You can share the CLK and SDO line, but the SDI has different functionally depending on the working mode. 

    When accessing the registers, the SDI is used as normal SDI line, but when used to read the data in "CS MODE, 4-WIRE WITHOUT BUSY INDICATOR" the SDI is used as CS and each device needs its own Chip select signal as it can be seen in figure 61.

    Regards

    Joan

Reply
  • Hi ,

    Can I ask your schematic to understand what you are trying to do?

    But I think you are not going to be able to share the SDI, SDO and CLK lines with all three devices. You can share the CLK and SDO line, but the SDI has different functionally depending on the working mode. 

    When accessing the registers, the SDI is used as normal SDI line, but when used to read the data in "CS MODE, 4-WIRE WITHOUT BUSY INDICATOR" the SDI is used as CS and each device needs its own Chip select signal as it can be seen in figure 61.

    Regards

    Joan

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