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AD4001 SPI Configuration

Category: Datasheet/Specs
Product Number: AD4001

I am confused by the SPI options with the AD4001 and am hoping someone can give me feedback on the options.

Is it safe to connect 2x AD4001's in "CS MODE, 4-WIRE WITHOUT BUSY INDICATOR" along with an AD5674 on the same SPI bus?

The datasheet is pretty complicated, with the state of SDI, SCK, and CONV at different times determining the function of the communication.

I see that it suggests using CS MODE, 4-WIRE WITHOUT BUSY INDICATOR for the case of multiple AD4001 devices. I see it also has a daisy chain mode, and that the two options use different "chip select" lines.

What does SDO actually do in these modes?

If SDO on the AD4001 is actually active high or low while I am trying to talk to the AD5674 it would be bad, and I am struggling to figure out if my concern is valid.

In "CS MODE, 4-WIRE WITHOUT BUSY INDICATOR" mode, I think it says that it can share a bus, but I would love some clarity on how to avoid ending up with SDO going active high (or active low) due to activity on SCK. If it goes active high or active low just from SCK activity it would of course disrupt all hope of talking to another device.

I would also like to be able to test the high-Z mode, but that requires writing to the configuration register. I think that would require using daisy-chain mode rather than "CS MODE, 4-WIRE WITHOUT BUSY INDICATOR" because SDI needs to be sending data, but that implies to me that SDO will definitely always be going active high or active low when SCK is active -- how does that work? Is it hopeless to use a daisy-chain mode with other devices on the SPI bus?

Parents
  • Hi,  .

    We'll look into this and get back to you.

    Regards,
    Jo

  • Thanks very much! I partially simplified by adding an analog multiplexer to the frontend to eliminate one of the ADCs, but I still would like to use both an AD4001 and also a AD5674 with a MCU that only has one easily accessible SPI bus.

    I think from the best I can read that the "CS MODE, 4-WIRE WITHOUT BUSY INDICATOR" using SDI as a CS pin, I think that SDO becomes tri-state when CS (SDI) and CONV are both high based on Table 11.

    Table 11. State of SDO on Power-Up

    CNV SDI SDO
    0 0 Low
    0 1 Low
    1 0 Low
    1 1 High-Z

    I read this as saying if CNV and SDI are both high, then SDO will be tri-state and not interfere with the bus.

    I cannot figure out from the datasheet what "power-up" means here, whether for one conversion or for the whole device. When I read the communication spec for "CS MODE, 4-WIRE WITHOUT BUSY INDICATOR" I need to put a rising edge on CNV to initiate the conversion. It does say SDI must be high when CNV goes high so that it "initiates a conversion and forces SDO to high impedance".

    This all implies to me that even in "CS MODE, 4-WIRE WITHOUT BUSY INDICATOR" the SDO line is still active low except for the time when conversion is high but SDI is also still high, but there can't be clock signals on SCK in that time period or it will ruin the conversion.

    Please do let me know if you find some clarity on this, at the least it seems like Table 11 says I need CNV and SDI to both be high except when communicating, but somehow CNV is assumed to idle low in the timing diagram.

    Do I need to typically keep SDI and CNV high, but pulse CNV low for a short time to start the conversion, wait the conversion time, and then bring SDI low so that SCK works on the clock? And then other devices will be fine because CNV and SDI are typically both just held high?

    Apologies if this just makes it more confusing. I do now have evaluation boards for both in hand so I will also be trying to prototype it in hardware before pushing it down onto a design to be fabricated.

Reply
  • Thanks very much! I partially simplified by adding an analog multiplexer to the frontend to eliminate one of the ADCs, but I still would like to use both an AD4001 and also a AD5674 with a MCU that only has one easily accessible SPI bus.

    I think from the best I can read that the "CS MODE, 4-WIRE WITHOUT BUSY INDICATOR" using SDI as a CS pin, I think that SDO becomes tri-state when CS (SDI) and CONV are both high based on Table 11.

    Table 11. State of SDO on Power-Up

    CNV SDI SDO
    0 0 Low
    0 1 Low
    1 0 Low
    1 1 High-Z

    I read this as saying if CNV and SDI are both high, then SDO will be tri-state and not interfere with the bus.

    I cannot figure out from the datasheet what "power-up" means here, whether for one conversion or for the whole device. When I read the communication spec for "CS MODE, 4-WIRE WITHOUT BUSY INDICATOR" I need to put a rising edge on CNV to initiate the conversion. It does say SDI must be high when CNV goes high so that it "initiates a conversion and forces SDO to high impedance".

    This all implies to me that even in "CS MODE, 4-WIRE WITHOUT BUSY INDICATOR" the SDO line is still active low except for the time when conversion is high but SDI is also still high, but there can't be clock signals on SCK in that time period or it will ruin the conversion.

    Please do let me know if you find some clarity on this, at the least it seems like Table 11 says I need CNV and SDI to both be high except when communicating, but somehow CNV is assumed to idle low in the timing diagram.

    Do I need to typically keep SDI and CNV high, but pulse CNV low for a short time to start the conversion, wait the conversion time, and then bring SDI low so that SCK works on the clock? And then other devices will be fine because CNV and SDI are typically both just held high?

    Apologies if this just makes it more confusing. I do now have evaluation boards for both in hand so I will also be trying to prototype it in hardware before pushing it down onto a design to be fabricated.

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