AD4001 SPI Configuration

Hi, Brian Neltner .

We'll look into this and get back to you.

Regards,
Jo

Thanks very much! I partially simplified by adding an analog multiplexer to the frontend to eliminate one of the ADCs, but I still would like to use both an AD4001 and also a AD5674 with a MCU that only has one easily accessible SPI bus.

I think from the best I can read that the "CS MODE, 4-WIRE WITHOUT BUSY INDICATOR" using SDI as a CS pin, I think that SDO becomes tri-state when CS (SDI) and CONV are both high based on Table 11.

Table 11. State of SDO on Power-Up

I read this as saying if CNV and SDI are both high, then SDO will be tri-state and not interfere with the bus.

I cannot figure out from the datasheet what "power-up" means here, whether for one conversion or for the whole device. When I read the communication spec for "CS MODE, 4-WIRE WITHOUT BUSY INDICATOR" I need to put a rising edge on CNV to initiate the conversion. It does say SDI must be high when CNV goes high so that it "initiates a conversion and forces SDO to high impedance".

This all implies to me that even in "CS MODE, 4-WIRE WITHOUT BUSY INDICATOR" the SDO line is still active low except for the time when conversion is high but SDI is also still high, but there can't be clock signals on SCK in that time period or it will ruin the conversion.

Please do let me know if you find some clarity on this, at the least it seems like Table 11 says I need CNV and SDI to both be high except when communicating, but somehow CNV is assumed to idle low in the timing diagram.

Do I need to typically keep SDI and CNV high, but pulse CNV low for a short time to start the conversion, wait the conversion time, and then bring SDI low so that SCK works on the clock? And then other devices will be fine because CNV and SDI are typically both just held high?

Apologies if this just makes it more confusing. I do now have evaluation boards for both in hand so I will also be trying to prototype it in hardware before pushing it down onto a design to be fabricated.

Dear Jo,

Is there any hope of getting a clarification on this in the next few days? I need to make a choice whether to use this family of parts or find one that I am more confident that the communication will work for.

This part looks excellent and I have already designed a front-end specifically for it, but I cannot risk making a PCB and finding after the fact that it cannot share a SPI bus.

I will have to decide by tomorrow, it's unfortunately been 2 weeks and I have to move this project forward. This is the only thing left holding me up, whether I can have this AD4001 (or any other parts in this pin-compatible family) on the same SPI bus as my AD5674 DAC.

Thanks!

Brian Neltner ,

I think the best way to understand how the SPI is used in "CS MODE, 4-WIRE WITHOUT BUSY INDICATOR" is to have a look to the timing diagram provided in the datasheet.

As you can see in this mode the SDO lines are in Hi-Z mode all the time except when they are transferring data. 

In this case the SDI lines are used as Chip select and the must be high during the rise edge of CNV and also make sure that you bring high SDI line before the conversion time elapses. After this time, you can pull down SDI (CS) of the ADC you want to read data from.

In this configuration if you want to read or write the registers then you need to pull down CNV and write the correct register access command:

Regards

Joan

Thank you for the clarification, it was not obvious to me that the straight flat lines were meant to indicate tristate.

Could you please explain how to send and receive data from the second chip assumed to be attached?

If I assume that SCK and SDI will have active digital data on them, can I just hold CNV high or low to prevent the chip from reading the SDI value as a CS signal?

I see that you hold SDI high when you raise CNV, which makes me think I can just keep CNV low.

The second example uses CNV as a CS line though, which makes holding it low sound bad. Based on the second diagram I feel like I need to hold CNV high in order to keep it from responding to SCK/SDI. Especially since SDI is also held high through the CNV edges in the second example, so the thing I see is CNV held high during communication in Example 1 but held low in Example 2 with the difference only being in how long.

I wish this was more obvious to me, I am probably overthinking it. I see a dozen chips or more between you and TI that all have similar looking diagrams but they all confuse me for the same reason. Do you have any example circuits showing this device in a SPI bus with a second device that shows how to do it? I just did the obvious, but I have solder jumpers everywhere because I still don't trust this datasheet's information.

I think I am totally failing to grasp the combinatoric logic used to configure the serial communication.

HiBrian Neltner ,

Can I ask your schematic to understand what you are trying to do?

But I think you are not going to be able to share the SDI, SDO and CLK lines with all three devices. You can share the CLK and SDO line, but the SDI has different functionally depending on the working mode. 

When accessing the registers, the SDI is used as normal SDI line, but when used to read the data in "CS MODE, 4-WIRE WITHOUT BUSY INDICATOR" the SDI is used as CS and each device needs its own Chip select signal as it can be seen in figure 61.

Regards

Joan

Thanks for the clarification, it sounds like it requires its own SPI bus.

That's actually my entire question, so I will mark that as the answer.