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AD7779 Recommended for New Designs
The AD7779 is an 8-channel, simultaneous sampling ADC. There are eight full Σ-Δ ADCs on chip. The AD7779 provides an ultralow input current to allow...
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AD7779 on Analog.com

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DRDY not in sync between two daisy-chained ADCs



		

			

									
					    vlgSkipper
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Sep 9, 2024 
				
			
			
		
    

				
		
    
		    		    
		    
		    		      		            		        
    Category: Hardware
    
    		        		            		    
    Product Number:  AD7779  
    
    		        		    		    	
			
    Hello,
    

    I'm trying to daisy-chain two devices (on eval board). I followed the datasheet on the subject :
    

      

    1.  MCLK is shared from U1 to U2 (generated by Y2 on the eval board)
      2. 

    2.  Reset is pulsed on both devices by a GPIO of an external MCU
      3. 

    3.  SPI configure DOUT_FORMAT to 0x80 on both ADC
      4. 

    4.  ODR is set
      5. 

    5.  START is pulsed on ADC U1
      6. 

    

      
    

    My problem is that U2 and U1 aren't in sync, more precisely they start synchronized and then U2 start to acquire data 1Hz faster or slower or just lag a bit behind U1.
    

    What did I missed? I already checked MCLK connexion.
    

    Best regards,
    

    
									
			        
		
    

				
						
        

    
    Tags: 
                                            
                 hardware
                
                                                    
                 ad7779
                
                                                    
                 Simultaneous Sampling A/D Converters
                
                                                    
                 AD7779 FMCZ
                
                                                    
                 Precision A/D Converters
                
                                        
                                            
                
                
                                
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                on Sep 10, 2024 4:49 AM
            
            
												
						in reply to JEstayo
					
									
        
	
        

		
		
        
					
        Hi JEstayo,

        Yes I wired two evaluations boards with jumper wire. I said previously, MCLK was my main concern but I will get an proper cable for this signal today.
        

        Below the test setup, with U1 and U2 being eval board, we monitor DRDY on both board with an oscilloscope.

         

        The configured register are the following : 
        

          

        1. DOUT_FORMAT (0x14) set to 0x80.
          2. 

        2. SRC is not set, we tried to set it but this didn't change our problem.
          3. 

        

        With a shared MCLK, DOUT_CLK are the same (frequency and in-phase) but DRDY are differents.
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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        •  Analog Employees  
        
            
						
                            
            
            				
            
                on Sep 11, 2024 1:48 AM
            
            
												
						in reply to vlgSkipper
					
									
        
	
        

		
		
        
					
        Hi, 
        

        Can you please provide the below waveform in a single capture?
        

        DRDY1, DRDY2, DCLK1, DCLK2, SYNC_OUT?
        

        If you have OSC with 4 channels, please take two captures. (DRDY1, DRDY2, DCLK1, SYNC_OUT /// DRDY1, DRDY2, DCLK2, SYNC_OUT, )
        

        Thanks 
        Vishnu 
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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                on Sep 11, 2024 12:02 PM
            
            
												
						in reply to VishnuNambrath
					
									
          
	
          

		
		
          
					
          Hi,

          After double checking everything (solder and jumper) we solved the problem.
          We used GPIO2/GPIO1/GPIO0 to sync the SCR update (added during our test) and it worked.

          U2 register 0x60 to 0x63 had wrong value at start-up or if we wrote theses register then used SRC_UPDATE reg.

          Thanks for the help, looks like it was my fault.
          

          Best regards
          
			
          

		
			
	      

		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

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