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AD7705

Category: Hardware
Product Number: AD7705 Variation in the H time of DYDR, AD7705

Hello

The AD7705 is operated with the settings CLKIN=1MHz, CLKDIV=0 Data rate 20Hz.
The channel is switched under the above conditions to read out the data.
The measurement results show that there is a bias in the H time of DYDR.
However, I am only switching the channel, so I do not understand the reason for this bias.

The yellow on the graph is DYDR and the green is CS.


Thank you.

  • Hello  ,

    /DRDY hold time can vary when no data read has taken place between output updates. You can notice that there was an available data, which is unused, between /CS pulses. By the way, the /CS pin should be held low for the whole read/write operation.

    If a data was not read, /DRDY will be held high for 500 clock cycles.

    Regards,

    Yugel