ADC AD4134

Hi yuanciou ,

The output data stream is framed by the ODR signal, the frequency of which matches the output data rate. Can you use the ODR signal?

Thanks,
Janine

Hi JEstayo : 

I already uesd ORD to control AD4134.

I want to make sure when does the AD4134 conversion complete that I catch the data is correct.

Is the ODR's high to low timing  AD4134 conversion time?

Hi yuanciou ,

Are you operating in ASRC *secondary mode? In *secondarymode, the ODR pin is input to the AD4134 and the ODR is set by providing a clock or pulse train at the desired ODR frequency (fODR) to the ODR pin.

The ADC employs oversampling, and samples the analog input continuously and at the rate of the *Main Clock, the data is then averaged in the digital filter. 

The data will be available t3 seconds from the falling edge of ODR. You can enable the status header to check for chip errors and if the filter has fully settled.

Thanks,
Janine


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Hi JEstayo : 

Firstly , the picture 1 which I used FPGA  to control AD4134.

Secondly ,  I set the AD4134's register form the picture 2 to picture 7 .

AD4134's pin50 connect to gnd.

I designed a periodic signal every 8Khz to read AD4134's data.

JEstayo , Dose the data  be available from falling edge of ODR? How to make sure that is correct? where can I find the information about that?

At AD4134 register address 0x11 "DATA_PACKET_CONFIG" which frame I set 24bit-ADC only.

picture 1 : 

picture 2 : 

picture 3 : 

picture 4 : 

picture 5 : 

picture 6 : 

picture 7 : 

picture 8 : 

picture 9 : 

Hi yuanciou ,

If you are using gated DCLK, please refer to Figure 2 in the timing section. for Free running DCLK, figure 3 will then be applicable. This is for the time from the ODR pulse to the LSB. Which DCLK mode are you using?

Thanks,
Janine

Hi JEstayo : 

I uesd Figure 2. Timing Diagram of Data Interface with Gated DCLK. 

Hi yuanciou ,

Please provide the ODR pulse desired and DCLK, and see if there is data after t3 seconds, provided the timing conditions in table 3 are met.

Thanks,
Janine

Hi JEstay :

The timing  table 3 ' t3 is 8ns (minimum).

picture 1 which I set is 31ns.

picture 1 : 

Thanks for capturing this, yuanciou ,

Going back to your concern initially, are there any reasons to believe the data in the DOUT is incorrect?

Hi JEstayo : 

(1) are there any reasons to believe the data in the DOUT is incorrect? -> yes

(2) I want to know how do  I  make sure that ADC4134 convert analog  voltage into Digital value completely ?  just like ADI ADC AD7608 has busy signal that telling ADC is conversion completely.

Hi JEstayo : 

(1) are there any reasons to believe the data in the DOUT is incorrect? -> yes

(2) I want to know how do  I  make sure that ADC4134 convert analog  voltage into Digital value completely ?  just like ADI ADC AD7608 has busy signal that telling ADC is conversion completely.

Hi yuanciou ,

(1) Can you please elaborate on why you believe data is incorrect?

(2) The AD4134 does not have a busy signal or data ready pin. The timing diagram will provide guidance when the data is ready. Additionally, you can append the status bits, and data is settled when PLL is locked, and filter is settled in the header.

Thanks,
Janine