AD7091 return wrong value

Hi, jhpark1 .

I think you are getting the correct values. You have stated that when 500 mV is the input, you are getting a decimal value of 820, right? But that is how it should be. AD7091 uses a straight binary conversion. I am assuming you are using its internal reference, 2.5V, right? Then, this is how it was calculated.

[Vin/Vref] x [2^N]

[500 mV/ Vref] x [2^12] = 819.2 or 820.

On the other hand, on your scope shot, it seems that SCLK lacks 4 pulses. I am seeing 12 SCLK pulses. It should be 16 SCLK cycle.  Are you using a custom eval board and controller board? If yes, would you mind sharing your schematic and the flow of your code from your bin file?

Regards,
Jo

Hi.

I'm using AD7091(exactly, AD7091BCPZ) not AD7091R.

Following the datasheet, reference is provided by VDD. (https://www.analog.com/media/en/technical-documentation/data-sheets/AD7091.PDF) So I thought ref is 5V.

I just followed because it was explained using 12 SCLK in the datasheet. I'll try with 16 SCLK.

Schematic I use is same with typical connection diagram in datasheet. (Not using pull-up resistor on SDO)

Hi, jhpark1 .

Apologies for missing some details from your thread. You are actually right with its VDD as its VREF (5V) and timing diagram for having 12 SCLK pulses. I was looking at the AD7091R-x family instead of AD7091. Let me correct this one for you. I'll get back to you in a while.

Best regards,
Jo

Hi, jhpark1 .

Can you iterate here how did you implement the software reset on the device? Also, may I know how long the CNVST and Conversion time is? Can you try probing on VDD and check what is the voltage across it? Let me know other details so I can further help you. 

Regards,
Jo

This is my reset code.

CONVST low time is 600ns. And after 1us, CS goes low.

I checked VDD with oscilloscope. It's about 5.02v

Hi, jhpark1 .

VDD seems fine. CNVST low time also satisfies the condition of being pulled up before EOC. Can you share your schematic? What is your signal source? 

On the other hand, I noticed on your timing diagram that you are using Mode 0 (CPOL=CPHA=0). Please ensure that your timing satisfies the condition of t12, the delay from the end of a conversion until the CS falling edge delay. And t10, the delay from CS falling edge until SDO exits the three-state condition. Lastly, the data is available from t2, data access time after SCLK falling edge.

Warm regards,
Jo