Category: Hardware
Product Number: max14001
The MAX14001 timing sequence diagrams were followed to implement write and read methods for the MAX14001 data registers via SPI. Setup is as an ADC only.
The MAX14001PMB eval board test initialization code is below. Thus, the hardware setup is correct. The issue: data reads from the registers are inconsistent. Every other read sequence in the test while() returns a value that is 0x200, 0x204, 0x203, 0x208, 0x100 or 0x000. The other reads return measurement data. The SPI clock rate is 1Mhz.
Thanks,
// Test initialization
bool MAX14001::MAX14001_Initialize() {
// Delay 200ms, per the chip configuration sequence flow chart, on power up
delay(200);
MAX14001_write(MAX14001_WREN_addr, 0x294);
MAX14001_write(MAX14001_FLTEN_addr, 0x7e); // disable MVL and FET
MAX14001_write(MAX14001_CFG_addr, 0x0c); // Set filter to x8
MAX14001_write(0x10 + MAX14001_WREN_addr, 0x294); // write verification register
MAX14001_write(0x10 + MAX14001_FLTEN_addr, 0x7e); // write verification register
MAX14001_write(0x10 + MAX14001_CFG_addr, 0x0c); // write verification register
while(1) {
MAX14001_read(MAX14001_ADC_addr);
delay(1000);
}
}
uint8_t MAX14001_read(uint8_t Register) {
uint16_t dataReceived;
uint16_t registerToRead = (uint16_t) ((((uint16_t)Register) << 11) & 0xf800 );
/* Visually verify the above operation */ (void)printf("MAX14001_read() -> Register: 0x%02x\n\n", ((registerToRead >> 11) & 0x001f));
MAXspi->beginTransaction(SPISettings(spiClk, MSBFIRST, SPI_MODE0));
//Pull SS low to prep other end for transfer
digitalWrite(SS, LOW);
(void)MAXspi->transfer16(reverse_uint16(registerToRead));
digitalWrite(SS, HIGH);
delay(1);
digitalWrite(SS, LOW);
dataReceived = reverse_uint16(MAXspi->transfer16(reverse_uint16(registerToRead)));
digitalWrite(SS, HIGH);
MAXspi->endTransaction();
(void)printf("MAX14001_read() -> Masked Read Data, Reversed: 0x%03x\n\n", dataReceived & 0x3ff);
return(dataReceived);
}
uint8_t MAX14001_write(uint8_t Register, uint16_t data) {
uint16_t dataReceived;
uint16_t data_to_send = (uint16_t)(((((uint16_t)Register) << 11) & 0xf800 ) + data + 1024); // 1024 sets write bit
// SPI data mode 0, also known as "data on leading edge" mode, is a common mode for Serial Peripheral Interface (SPI)
// bus communication. In this mode, the clock starts with a low-level pulse (CPOL = 0), and data is sampled
// on the leading (falling) edge of the clock signal (CPHA = 0). This means that data is stable on the first clock
// edge and changes on the second.
MAXspi->beginTransaction(SPISettings(spiClk, MSBFIRST, SPI_MODE0));
//Pull SS low to prep other end for transfer
digitalWrite(SS, LOW);
// Return the Register address preceded by the write bit - this is returned LSB first.
// ...12 13 14 15 16
// ...W A0 A1 A2 A3
dataReceived = MAXspi->transfer16(reverse_uint16(data_to_send));
//Pull SS high to signify end of the data transfer
digitalWrite(SS, HIGH);
MAXspi->endTransaction();
/*Test print to verify the correct address bit placement */
(void)printf("MAX14001_write() -> Write Register: 0x%02x\t Received Register: 0x%02x\n", (Register & 0x3f),
(uint8_t)(dataReceived & 0x003f));
return(dataReceived);
}
