Reading Data with 10MHz SPI Clock

Hi, zsa .

May I know what FPGA are you using? Can you share a data or scope shot of your timing diagram? Also, I would like to make clarification on what timing diagram, from its datasheet, are you referring to? You can also iterate how do you readback the configuration register.

You can also use the design file available from its product page as your reference for your custom board: EVAL-AD7949 Evaluation Board | Analog Devices

Warm regards,
Jo

https://digilent.com/reference/programmable-logic/arty-a7/start
I am using the FPGA development kit in the link. (Main clock is 100MHz, SPI Clock is 10MHz)

At the same time, I am sending data from the logic analyzer and listening to the interface.

I added the diagram I used to the image below. (GENERAL TIMING WITHOUT A BUSY INDICATOR )

I am already iterating the readback for 1 second. 

There are also pull-up and pull-down resistors at the output of interface. Resistors and their values same as the picture below. Will this be a problem?

Hi, zsa .

While looking into your query, may I also ask how long is your CNV high?

You can also use this timing diagram.

Regards,
Jo

CNV remains high for 2.5us
I think the reason why it is not reading is related to the pull-up and pull-down resistors we put on the interface outputs.