AD7770 MEMMAP_CRC_ERR Occurence

Hi Yuki. ,

After reading the MEMMAP_CRC_ERR to be set, can you confirm the register values are the same with what you have written?

Please perform a register read before and after the bit sets and share the result here. 

Yuki. said:

*2 This does not occur when an error check (reading GEN_ERR_REG_1) is performed for each write to one register in (3).

Can you please confirm this does not occur when you write to one of the registers, but only occurs when you write to 16 registers you listed?

Thanks,
Janine

Hi JEstayo,

thank you for your support.

JEstayo said:

After reading the MEMMAP_CRC_ERR to be set, can you confirm the register values are the same with what you have written?

The following procedure was used to confirm the results.

1) Executed setting value writing to 16 registers
2) Executed reading of 16 registers  => Confirmed that the read values matched the written values
3) Executed reading the MEM_CRC_err flag => Confirmed that an error occurred
4) Executed to read 16 registers =>  Confirmed that the read values are the same as the written values

The following is the data of the registers.

CH0_CONFIG ~ CH7_CONFIG(0x000~0x007) => 0x00
GENERAL_USER_CONFIG_1(0x011) => 0x74
GENERAL_USER_CONFIG_2(0x012) => 0x08
ADC_MUX_CONFIG(0x015) => 0x40
SRC_N_MSB(0x060) => 0x00
SRC_N_LSB(0x061) => 0xC8
SRC_IF_MSB(0x062) => 0x00
SRC_IF_LSB(0x063) => 0x00
SRC_UPDATE(0x064) => 0x01

JEstayo said:

Can you please confirm this does not occur when you write to one of the registers, but only occurs when you write to 16 registers you listed?

As a result of confirmation, this occurred when consecutive writes were executed to two or more registers.

Best Regards,
Yuki.

Hi Yuki. ,

When you write to consecutive registers, what is the frame size of your SPI transactions?

Thanks,
Janine

Hi Janine,

The frame size is 8bits.

Best regards,
Yuki.

Hi Yuki. ,

Can you please verify that the timing specifications in table 3 are met? 

After writing to the decimation registers, please set the bit SRC_LOAD_UPDATE high for at least two MCLK periods and return the bit to 0 before attempting another update. Please share your entire register settings also.

Thanks,
Janine

Hi Janine,

> After writing to the decimation registers, please set the bit SRC_LOAD_UPDATE high for at least two MCLK periods and return > > the bit to 0 before attempting another update. 

I tried this, but it did not improve.

> Can you please verify that the timing specifications in table 3 are met? 

The timing meets the spec.

PDF

I will share the register settings.

PDF

Best Regard,
Yuki.

Hi Janine,

Thank you for your support.

I received an email from the Engineer Zone on October 3rd, but I already replied to your question on September 30th. Please check my reply.

Best regard,
Yuki.

Hi Yuki. ,

Apologies for the delay in response.

The registers that are marked red, does this mean these registers have different values from the default even when you did not write on them? The Gain registers seem to be all 1s. Is this the correct setting?

Can you reset the ADC and check again?

Thanks,
Janine

Hi Janine,

Thank you for your support.

As you understand, the registers marked in red have values that differ from the default, even though no writes have been made.

It didn't change even after resetting.

Best regard,
Yuki.

Hi Yuki, 

How did you perform the reset? Did you pull the reset line to low or write 1 to SOFT_RESET?

Normally all registers should go to the default value either way. 

Regards 
Vishnu