Hi everyone,
Nice to meet you all! I am a university student studying in Korea and I am still a complete beginner. So, please don't look at my question too harshly and I would be extremely grateful for any advice or solutions you can provide.
Currently, I am using the Zynq-Z2 board and analyzing the AD7476A included in the Pmod AD1.
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I have confirmed from the datasheet that the AD7476A can achieve a maximum sampling rate of 1Msps with an SCLK of 20MHz. However, I want to verify this sampling rate in Jupyter. How can I do this?
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Is my understanding of the SCLK correct? Is it correct to divide the main frequency of the FPGA, which is 100MHz, down to 20MHz for use?
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For example, if I want to achieve a sampling rate of 100KHz instead of the maximum 1Msps and verify this in Jupyter with Python, what steps should I follow?
In short, I need a way to clearly confirm the sampling rate visually.
Thank you so much for your help!
