AD7124 MCLK

Hi howardaaa ,

The AD7124-8 includes an internal 614.4 kHz clock on chip. This is the MCLK or Master Clock frequency equal to 614.4 kHz. However, this clock is internally divided, where the division factor being dependent on the power mode. Thus, the range of output data rates and performance is affected by the power mode.

You may also refer to the Table 52. Power Modes of the datasheet which also supports the page 11 timing characteristics table 4 you were referring to.

Thanks and regards,

Rod

Hi howardaaa ,

The AD7124-8 includes an internal 614.4 kHz clock on chip. This is the MCLK or Master Clock frequency equal to 614.4 kHz. However, this clock is internally divided, where the division factor being dependent on the power mode. Thus, the range of output data rates and performance is affected by the power mode.

You may also refer to the Table 52. Power Modes of the datasheet which also supports the page 11 timing characteristics table 4 you were referring to.

Thanks and regards,

Rod

Hi,

do you mean that at Mid Power, MCLK=153.6kHz?

But I think it's still 614.4k, because in the equation the numerator has changed from 3 to 12,

and 12/614.4k=3/153.6k.

Hi howardaaa ,

Apologies for the confusion. Yes, you are correct, the MCLK value to be used for the page 11 timing characteristics table 4 is 614.4kHz for the different power modes. 

Regards,

Rod