On the AD7770 dev kit what are the register settings for 32kHz sampling rate. Even with a divisor of 1 the sampling rate is 16kHz. There must be an additional setting.
AD7770
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The AD7770 is an 8-channel, simultaneous sampling ADC. Eight
full sigma-delta (Σ-Δ) ADCs are on chip. The AD7770 provides
a low input current to allow...
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AD7770 on Analog.com
On the AD7770 dev kit what are the register settings for 32kHz sampling rate. Even with a divisor of 1 the sampling rate is 16kHz. There must be an additional setting.
Hi davec ,
Can you check the details below and get back? Thanks.
1. Share your register settings
2. Try changing the ODR using the input value in the eval SW, then reading the register
3. Verify MCLK frequency
Thanks,
Janine
Hi davec ,
I tried writing 64 (0x40) to the SRC_N_LSB register and was able to get 64kHz ODR.
ODR, high resolution = (MCLK/4) / Dec_rate = (8.192MHz/4) /(64) = 32 kHz
Can you please try to write this value?
Thanks,
Janine