Synchronizing multiple AD4858

Hi punee995 ,

If you want to connect three (3) AD485, you can share the CMOS interface but have a dedicated CS line per device. And for the SCKI and SCKO are similar to the SCKL configuration, you can refer to the picture below as your reference. 

Thank you and regards,
Jo

Hi Jo,

Thank you for your response.

    As I mention earlier, we are planning to use LVDS/CMOS Conversion Data Bus. for the SPI will restrict us to achieve 1MSPS/channel throughput for 3 ADCs because SPI CSCK Period for AD4858 is 40ns. 

    We are planning to use LVDS Conversion Data Bus. In that case how do you suggest synchronizing clocks for all 3 ADCs?

Regards,

Punit Patel

Hi punee995 ,

It is pretty much the same configuration as shown in the figure above if you will be using LVDS.

Best regards,
Jo

Roger that, I guess we will use clock buffer to avoid clock stub and Signal Drive strength issue.

Hi, punee995 .

Just want to correct my previous response. The configuration is not the same as given above. For LVDS, I just confirmed from the product owner that you will be needing dedicated LVDS per port of AD4858. Let me know other details of your application so I could further assist you. Thank you for your patience.

Warm regards,
Jo

I have created top level block diagram for interfacing 3 AD4858 please let us know if I missed anything. As stated before, we need time sync between all 3 ADCs. so, All ADC can Sample Data at the same time.

Hi punee995 ,

Apologies. We made a confusion for the proper connection. We just verified the connection, along with the product owner, and the correct way to connect them is similar to the figure I have attached before. Please refer to that figure. Once again, thank you for being patient. Feel free to post here whenever questions arise regarding to this thread. 

Warm regards,
Jo

Noted, Thank you for your response. 

Noted, Thank you for your response.