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AD7175-2: Large settling delay at ADC input

Category: Hardware
Product Number: AD7175-2

Hi,

I am having issues with the settling time of the ADC input channels AIN1 and AIN0.

AIN0 receives a positive input and AIN1 is connected to the ground.

The filter used is the same as the one used in the EVAL board.

The ADC outputs a higher conversion result value after the input steps down from 2.3V to 0.4V. 

It is always the first conversion result that is incorrect.

Applying a delay of approximately 500ms between the ADC reading after the voltage step down resolves this issue but sometimes you still have an incorrect result.

I have tried running the ADC from 10SPS to 1000SPS in continuous conversion mode, and the issue still exists in all the results.

I have also scoped the step-down input and it usually settles within a few microseconds.

Please advise on anything I could try to reduce the delay.

Thank you.



added the part number to the subject field
[edited by: JEstayo at 1:48 AM (GMT -5) on 6 Mar 2024]

Top Replies

    •  Analog Employees 
    •  Super User 
    Mar 10, 2024 in reply to JCCillion +2 verified

    Hi  ,

    When a step change occurs on the analog input, the digital filters will need to settle on the new analog input. If the step-change in analog input occurs exactly at the start of a digital filter…

    •  Analog Employees 
    •  Super User 
    Mar 27, 2024 in reply to Bilal71 +1 verified

    Hi  ,

    Setting the SING_CYC bit allows the ADC to output only fully settled data by reducing the output data rate to be equal to the settling time of the ADC for the selected output data rate. When…

  • Hi  ,

    I am currently looking into this. I will get back to you soon.

    Regards,

    JC

  • Hi  ,

    When a step change occurs on the analog input, the digital filters will need to settle on the new analog input. If the step-change in analog input occurs exactly at the start of a digital filter sampling period then the output code would have settled the third RDY pulse for sinc3 and fifth RDY pulse sinc5+sinc1.

    However, a step change on the analog can occur at any point in the interval between two RDY pulses, so in general, the step-change will not occur at the start of the filter sampling period. This means the output code will not have settled by the third RDY pulse but will have settled by the fourth RDY pulse in the case of sinc3. Similar would happen for sinc5+sinc1, the output code will not have settled by the fifth RDY pulse but will have settled by the sixth RDY pulse.

    How many channels are enabled in your setup? Aside from the anti-alias filters in the input, are there any other external circuit that may need to settle? Depending on the external circuit, a settling time is required to ensure that the input is fully settled. 

    You may also want to check our available tool Virtual Eval | Analog Devices. The tool includes the timing of the ADC at different ODR and the step response.

    Regards,

    JC

  • Hi JC,

    Thank you for your reply.

    Your explanation makes sense and I am seeing better results by implementing your suggestions.

    I just had a question regarding the filter settling time, would setting the SING_CYC bit in the ADC mode register automatically take care of the filter settling time or should I still wait until the 5th RDY pulse?

    Thank you,
    Bilal

  • Hi  ,

    Setting the SING_CYC bit allows the ADC to output only fully settled data by reducing the output data rate to be equal to the settling time of the ADC for the selected output data rate. When a step change between two RDY pulses occur and SING_CYC bit is enabled, the output code will be settled at the 2nd RDY pulse. One thing to note that this bit has no effect with the sinc5 + sinc1 filter at output data rates of 10kSPS and lower.

    Regards,

    JC