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ad7980 in 3 wire mode obseriving pulse on VIO

Category: Hardware
Product Number: AD7980


We are using the AD7980 in the 3-wire mode without busy indicator where we have SDI tied to VIO (3v3), in our operation we turn on the VDD (2v5) before we turn on the VIO, and REF is at 5V. When we power VDD before VIO, during the period before VDD is turned on, we see square waves being sent out from the VDD pin causing an immense amount of noise in the system, are these square waves potentially from the SDI pin? If yes, what is the best way to eliminate this issue? Our power-up sequence is VDD (2v5), VIO (3v3) next, and REF (5v) last.

If I understand the datasheet correctly, the "When VIO is greater than or equal to VDD, the AD7980 is insensitive to power supply sequencing" statement, made us not consider the power sequence. Is there something we should be carful about?

Thank you for your help in advance!

  • Hi,  .

    Based on what I understand, you are getting samples during the period before VDD is turned on right? And that is before initializing VREF and VIO and letting the device settle. So, I think the noise is coming from the inrush current during the initialization. I would suggest getting samples after the device has been fully powered up and has already been settled.

    Also, try initializing the VREF before VIO. Since the analog input is dependent to its VREF:
    Vdd -> Vref -> Vio -> Let the device settle.

    Let me know if this will help you so I could further assist you.

    Warm regards,

  • Thank you for getting back,  .

    I believe we are not initializing SPI before all voltages are turned on (but I will double-check that), so we should not get any samples during the period before VIO or VREF is turned on.

    The problem is we are getting a lot of noise on the VDD voltage rail which is then being coupled into other voltage rails (since all voltage rails are powered from the same input) and the ADC reading. After all voltages are turned on (in VDD -> VIO -> VREF sequence), the noise on the VIO rail persists as shown in the attached image from the scope. This is from our own board design where 3v3 (VIO) is generated with an LT8333, and the 3v3 is supplied to the VIO of AD7980 and V+ of ADHV4702-1.

    We will try the recommended power supply sequencing on our board and breadboard setup, and verify if SPI is initialized before all voltages are supplied.



  • Hi  ,

    I would also suggest putting a ground connection (maybe using a jumper connection from the test points) from your board to your signal generator and send us a scope shot.