LTC2508-32 SDOA pin output waveform is abnormal

Hi Timsen ,

I have few concerns in your query:

1) I noticed that you are using the correct supplies for Vdd and Ovdd. What is your Vref? Also, is RDLA already tied to ground before initializing the device? Can you try letting the Vref and Ovdd to be in their settling state before putting signal at the analog input? As you can see here, analog input pins are dependent on Vref. So, you need to power up first the Vref. After that, power up the Ovdd as the digital pins are dependent on it. Then let them settle first before putting signal to the analog inputs. Can you send a photo of the waveform after performing the power up sequence? If problem still persist, see no. 2.

2) Are you using a custom board? I have noticed that you used 30.1R to its input. But on its existing schematic, they used 10R and 0R.

3) I also noticed that you are using two LTC2508. If it is okay for you, can you show us the whole schematic? 

Thanks and regards,
Jo

Dear 

 Vref=5V，RDLA=0，Vref and Ovdd to be in their settling state. The resistance has been changed to used 10R.

But the SDOA waveform is still strange, and the converted data is also wrong?

Hi Timsen ,

Is there a way to contact you? So that you can send your schematic to us.

Thanks and regards,
Jo

PDFSee attachment for schematic diagram

Hello Timsen ,

We'll look into the schematic and get back to you.

Regards,
Jo

Hi Timsen ,

Can you send us a snapshot of your configurations? Also, can you try explaining to us the steps on how are you communicating with the ADC by listing it?

Thanks and regards,
Jo

Dear Jo:

      Fixed, because three LTC2508-32 pin 1 RDLA tablet selection problem, initially two LTC2508-32 valid, has been corrected.

Another issue: for pin 14 SYNC of LTC2508-32, the specification says that SYNC should be completed in one MCLK cycle.  But MCLK is 1M, the time between two MCLKS is 1us, the falling edge of DRL is almost 650ns, MCU triggers the interrupt, and then pull the high level has passed 1us.  What do we do with this?  What is your suggestion? 

Hello Timsen ,

We are still looking at your query. Thank you for the patience.

Warm regards,
Jo

Hi Timsen 

You need to make sure then synch pulse occurs before the new MCLK cycle as indicates the timing diagram, if this is not the case, we cannot guarantee a proper synchronization.

 You will need to optimize the interruption routine to ensure the timing. You could also try to trigger the interrupt with the rising edge of DRL instead with the falling edge but make sure the SYNC goes high after the falling of DRL.

Regards

Joan