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# AD7768: How can the input bandwidth of ADC is lesser than output data rate?

Category: Hardware

I am seeking clarification regarding the fundamental technical terms "input bandwidth," "input sampling rate," and "output data rate" as used in the datasheet for the AD7768 sigma-delta ADC.

Input Bandwidth: The datasheet specifies the input bandwidth of the AD7768 as 110 kHz. Could you please provide a detailed explanation of "input bandwidth" in the context of an ADC? How does the input bandwidth impact the ADC's ability to accurately convert a range of input signal frequencies?

Input Sampling Rate: What is the typical range of "input sampling rate" for a sigma-delta ADC like the AD7768? Is the input sampling rate equivalent to the oversampling rate? How does the input sampling rate influence the ADC's performance and its relationship with the input bandwidth?

Output Data Rate: The AD7768 datasheet specifies the output data rate as 250 kSPS. How does this output data rate relate to the input sampling rate and oversampling? Considering the ADC has an input sampling frequency of 110 kHz, how is it able to generate an output data rate of 250 kSPS?

I would greatly appreciate any technical insights or clarifications you can provide on these terms and how they specifically apply to the AD7768 ADC.

Thanks

Deepak

Added the product number to the subject field
[edited by: JEstayo at 4:33 AM (GMT -5) on 19 Feb 2024]
• Hi  ,

Please refer to below for the answers, but please note that this will be specific to the AD7768. If you have other questions, let me know.

Input Bandwidth:
This is the maximum input signal frequency that the ADC can convert with acceptable attenuation (-3dB) Please refer to figures 89-90 to visually represent this digital filter response.

Input Sampling Rate:
After providing the master clock (MCLK) to the ADC, the modulator frequency is set in register 0x04 [1:0] . the MCLK division can be set to /4, /8, or /32, depending on the power mode, decimation rate, and base MCLK available. The Precision ADC Driver tool also suggests MCLK division as you vary the MCLK and power mode.

The sampling frequency is 2 x fMOD. This is the rate at which the input is being sampled. This is discussed further in detail in the Theory of Operation section of the datasheet.

Output Data Rate:

The Sigma Delta converter is an inherently oversampling converter. Performing the sampling at a very high frequency and outputs the data at a lower frequency through averaging and down sampling to push the noise out of the bandwidth of interest.

The output data rate is computed as fMOD/Decimation

The maximum output data rate of AD7768 is 256 kHz. This again relates to figures 89-90, showing the digital filter response when using Sinc5 filter, or Wideband filter. This also follows the nyquist theorem that states the output data rate must be at least twice the input frequency. Hence, the Pass Band (Input Bandwidth) is 0.4 x ODR for Wideband Filter, and 0.204 x ODR for Sinc5 Filter.

Below is a tutorial on the basics of sigma delta. However, the specific application to AD7768 will be found in the Datasheet: Theory of Operation section.

MT-022: ADC Architectures III, Sigma-Delta ADC Basics (analog.com)

Thanks,
Janine