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AD7265 - Could SCLK be IDLE = 0?

Category: Hardware
Product Number: AD7265

Hi!,

Could SCLK be used as IDLE = 0?

I mean to hold SCLK = 0 before CS falling edge, and hold SCKL = 0 before rising edge on CS.

I've prepared a drawng to clarify it:

I want to read both ADC outputs on the same pin, and need SCLK to be IDLE = 0 because some other ICs on the same SPI bus need it to be as that.

Thanks in advance for your support!. Regards.

Aldo.



EDITED: I have write DAC instead of ADC.
[edited by: Pepo12 at 7:13 PM (GMT -5) on 13 Feb 2024]

Top Replies

    •  Analog Employees 
    Feb 18, 2024 in reply to NathanT +1 verified

    Hello  ,

    Based on what I understand from your query, you are pertaining to the CPOL of the device right? If that would be the case, you will be needing to tweak few codes if you have a controller…

Parents Reply
  • Hello  ,

    Based on what I understand from your query, you are pertaining to the CPOL of the device right? If that would be the case, you will be needing to tweak few codes if you have a controller board that could be flashed by a binary file. You need to change the CPOL to 0 to be an active high. Since based on its datasheet, the SCLK's polarity is in active low. 

    On the other hand, we still recommend following the timing diagram from the datasheet since that is where the device has been tested to be in its optimal state.

    Thanks and regards,
    Jo

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