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AD7760 Low Power mode and low speed interface

Category: Datasheet/Specs
Product Number: AD7760

Hi, I have a  few questions on AD7760 operating in Filtered Output mode:
1. What operations can be performed while AD7760 is in Low Power mode? Obviously I can write to control register but can I read from Status Register or any other registers? Can I read last conversion value while AD7760 is in Low Power mode?
2.  Datasheet states that in order to read status and other registers "user must first write to the control register of the device, setting a bit that corresponds to the register to be read. The next read operation outputs the contents of the selected register instead of a conversion result." Does it mean that I should use timing diagram from Fig.2? But than we read two times 16 bits. Is the MSW part carrying status register data or the LSW+STATUS? Or should I perform only single read? Do you have timing diagram for status register read operation?
3. Datasheet indicates minimum timing requirements for parallel interface. Is there any limit on minimum speed of the interface? I know the read must be completed before next /DRDY signal arrives but when AD7760 is in Low Power mode the conversion process is halted. Assuming we can read data from AD7760 in Low Power mode, are there any restrictions on maximum timings?

Top Replies

    •  Analog Employees 
    Feb 12, 2024 in reply to DariuszA +2 verified

    Hi  ,

    Sorry for getting back just now. Please refer to the answers below and let me know if you have any questions.

    1. The registers and conversion result cannot be accessed when the ADC is in Power…

    • Feb 12, 2024 in reply to JEstayo +1 verified

      Hi  ,
      those answers are clear. Since ADC must be in Power Up mode in order to read conversion result or register data, the conversion rate is the natural window for read operation This defines slowest…

    • Hi,

      I'm looking into this and will get back to you.

      Thanks,
      Janine

    • Hi  ,

      Please refer to the answers below. Let me know if you have other questions.

      1. The ADC provides option to operate in low power mode to reduce power consumption with the trade-off of 6dB reduction in noise performance. You can still operate the ADC similarly to normal mode.
      2. Yes, you should use the timing diagram in figure 2. When reading the register  data, the next read operation outputs the contents of the selected register (16 bits)
      3. Minimum would be indicated as "min" in the unit column both specified for MCLK and ICLK, these specifications are the same for low power mode.

      Thanks,
      Janine

    • Hi JEstayo,
      thank you for prompt response. It is very helpful. I have couple more questions.
      1. What about Power Down mode? Can I write to registers and read back from those registers in Power Down mode? Can I read last conversion result (before chip entered Power Down)?
      2. On register reading: Timing on Fig.2 shows read of two times 16 bits. Which one contains register data, first or the second one?
      3. I think there is confusion on my side. When I said minimum speed of the interface I meant maximum timing. Is there any limit for maximum timing for the signals during the read process especially in Power Down mode when there is no conversion performed? 

    • Hi  ,

      do you have any update on my other questions about Power Down mode and how slow the interface can operate? I'd appreciate any information in this matter.

    • Hi  ,

      Sorry for getting back just now. Please refer to the answers below and let me know if you have any questions.

      1. The registers and conversion result cannot be accessed when the ADC is in Power Down Mode.

      2. The timing in figure 2 is for reading the data conversion. The 1st 16 bits is the 16MSBs, and the next 16bits contain the 8LSBs + 8 status bits. When reading the registers, you only need 1x 16 bits read and the next read operation will output the 16bit content of the selected register.

      3. Regarding the limit for maximum timing during the read process in power down mode, you still cannot read data or registers when the device is powered down.

      When you say maximum timing, can you clarify which timing you mean? The limitations in timing should be specified in table 3. If anything is unclear, please let me know which part.

      The ODR is dependent on the ICLK and digital filter configurations (please refer to table 6). While the ICLK is generated from the MCLK (Please refer to page 24)

      Thanks,
      Janine

    • Hi  ,
      those answers are clear. Since ADC must be in Power Up mode in order to read conversion result or register data, the conversion rate is the natural window for read operation This defines slowest possible interface, I presume. 
      thnak you very much. 

    • Hi  ,

      I'm glad to hear that. You are right that the natural window for read operation will be the ODR
      Please feel free to post another thread if you have other questions.

      Thanks,
      Janine