AD7476 operation mode

Hi millerd ,

We'll look into this and get back to you.

Warm regards,
Jo

Hi millerd ,

Is there a minimum number of SCLK for AD7476 in order to enter the power-down mode? Or can I high the CS after the second falling edge of the SCLK and disable the SCLK? Will the chip enter in power-down? The datasheet only says that to exit the power-down mode, you need to apply 10 SCLK and you can high the CS without 16 SCLK.

You are correct. You can enter the power-down mode after the 2nd falling edge of the SCLK. Also, you need to take note that as long as it is also before the 10th (tenth) falling edge of SCLK, then you can enter the power-down mode.

It is also said, if CS brought high before the 10 SCLK AD7476 go back to power-down mode. In this case, is it necessary to apply 16 SCLK to the chip when the CS is high?

In order to exit this mode (power-down mode), perform a dummy conversion. On the falling edge of CS, the device begins to power up, and continues to power up as long as CS is held low until after the falling edge of the tenth SCLK. The device is fully powered up once 16 SCLKs have elapsed.

Warm regards,
Jo

Thanks, but I wanted to know, do I need to supply  the SCLK  after CS has gone up to enter power-down mode? Or will only 2 falling edges be enough? As in the photo below.

Hello, millerd .

SCLK will still continue even in power-down mode. Since this mode is intended for use in applications where slower throughput rates are required.

And just in case you want to exit this mode (power-down mode), perform a dummy conversion. The device begins to power up once CS is pulled low and continues to power up as long as CS is held low until after the falling edge of the tenth SCLK. AD7476 will be fully powered up once 16 SCLKs have elapsed.

Thanks and regards,
Jo