ad7768 soft reset

This seems to be more a part related question. So move it to the precision ADC forum.

Hi,

I am looking into this and will get back to you.

Thanks,
Janine

Hi jay_col ,

The AD7768 driver should have a soft reset as well. In the current driver, the soft reset has to be sent manually via SPI or GPIO.

I am checking on how to implement this and will get back to you soon.

Thanks,
Janine

After posting this I realized its very similar to a previous question I asked here:  ad7768 eval start_n pin  and here  AD7768 GPIO controller seems unused 

The HDL design for this chip has a gpio controller.  I think the no-os version of the driver uses this controller to config start and reset on the chip.  I think maybe this is an oversight in the linux driver which is likely supposed to issue a reset via SPI during the driver probe.

Hi jay_col ,

Upon reviewing the ad7768 driver, I observed the presence of the .debugfs_reg_access function, facilitating communication with the register through IIO attributes.

For reading, the command is structured as follows:
iio_attr -D ad7768 direct_reg_access 0x1d

Regarding the write operation, initiating a software reset necessitates two writes to the SPI_RESET [1:0] bits. The sequence involves setting the bits initially to '11' and subsequently to '10' for the reset to take effect:
iio_attr -D ad7768 direct_reg_access 0x3
iio_attr -D ad7768 direct_reg_access 0x2
```

Let me know if this works for you.

Regards,
Michelle

Thanks, this is a good workaround.

I noticed that in later versions of the driver there are now bindings to map the gpio-based reset_n pin.  It's now documented in the devicetree bindings for the ad7768.