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AD4130- 8 power down mode

Category: Hardware
Product Number: AD4130- 8
Hi, I am using the AD4130 in the WLCSP package on my custom board. The standard way of operating is as follows:
  1.  Power on the device.
  2. Wait 2048us for the reset to perform.
  3. Soft reset the device (by writing 64 consecutive 1s to the device).
  4. Wait 2048us.
  5. Read the ID register content.
  6. SETUP registers:
    • CONTROL (SPI 4-wire, int_ref_en, data_status).
    • MISC (stby_refhole_en, stby_diagnostics_en).
    • ERR_EN(spi_write_err_en, spi_read_err_en, spi_ignore_err_en)
    • CONFIG (pga_gain).
    • FILTER (filter_mode_n = 2, fs = 2047).
    • CHANNEL (ainp, ainm, enable_m).
    • CONTROL (set single_con).
  7.  After the data_ready signal on the INT pin - I read data and status from the DATA register. If there is a master_err flag, I also read the ERRORS register and then write 0 to it to clear its content.
  8. SETUP registers:
    • CTRL (mode = STANDBY)
    • Wait 1ms
    • CTRL (mode = POWER_DOWN)
  9. Wait for some time (20sec) and then perform steps 1-8 again.
The first problem I've encountered is the fact that I can't wake up the device. The content of the ID reg is always corrupted. To fix this, I omit the last writing to the CTRL register (choosing POWER_DOWN mode). It helps, but it is not a solution that satisfies me.
Another problem is the content of the DATA register, which sometimes is not correct. 
Perhaps somebody can point out what I am doing wrong? Or does anyone have a similar problem with this ADC? Thank you in advance.





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