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Troubleshooting Bias voltages on AD5941

Thread Summary

The user is troubleshooting bias voltages for the AD5941, specifically how to set and validate the DC bias in the waveform. The final answer confirms that Vbias can be less than Vzero, and the voltage at SE0 w.r.t. GND is always Vzero, regardless of the SinAmplitudeWord value. The user should measure the DC bias by observing the voltage across CE0 and SE0, and can turn off the waveform generator (WG) to apply only the DC bias. The accompanying answers clarify that the electrode setup should be configured correctly, with RE0 and CE0 tied together for accurate measurements.
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Hello, 

I'm working on troubleshooting the bias voltages for AD5941. As per AD5941 - setting DC Bias to 0 and Gain to 1? - Q&A - Precision ADCs - EngineerZone (analog.com), the Vzero can go from 0.2 V to 2.4 V, and ad5940-examples/examples/AD5940_Impedance/Impedance.c at master · analogdevicesinc/ad5940-examples (github.com) currently has Vzero set to 1.1V. From here, Bias0 is set such that it's 1.1V + Bias Voltage.

I'm assuming Bias0 also has a range from 0.2V to 2.4V. As per the datasheet, SE will experience a bias voltage of Vbias - Vzero, which in case Vbias = 0, this will also be 0. Am I understanding this right? I verified this to be true by placing a DMM across Vbias and Vzero but wanted confirmation. 

My question lies in determining how I can validate this bias in the waveform. Without a bias, does the Waveform generator have a default bias of 1.1V? If the bias is present. for example: 

1. Bias = -100mV (i.e. Vbias - Vzero = -100 mV) - does this mean that the waveform at CE will have an offset of 1V instead of 1.1V? 

2. Bias = 100 mV (i.e. Vbias - Vzero = 100 mV) - does this mean that the waveform at CE will have an offset of 1.2V instead of 1.1V? 

I can see the differences between Vbias and Vzero, but I'm having trouble seeing how it would apply to the generated waveform from the HSDAC and quantifying that. If you have any advice to these questions along with how to better quantify and visualize the bias in the waveform, please let me know. 

Additionally, can you please explain the difference between the code for the bias in the Impedance example and the EIS one? The EIS one (ad5940-examples/examples/AD5940_ECSns_EIS/Impedance.c at master · analogdevicesinc/ad5940-examples (github.com)) utilizes the actual DAC codes, but the conversion formula in the datasheet differs from the actual code. It also doesn't follow the compensation code for the 12bit and 6bit outputs of the LPDAC recommended in the datasheet. Any explanation here would be appreciated. Thank you. 

Thank you for your time!

Edit Notes

Added a question about the EIS bias code and its comparison to the impedance code.
[edited by: kbaudue at 11:11 PM (GMT -5) on 14 Jan 2024]
  • Hi,

    In the example,

    1)

    Bias volts = VBIAS - VZERO

    VZERO = 1.1V

    Bias volts =0

    Hence, VBIAS = 1.1V

    2)

    Voltage of CE0 with respect to ground = VBIAS (If SinAmplitudeWord = 0)

    Voltage of SE0 with respect to ground = VZERO

    3)

    If SinAmplitudeWord is not 0,

        Sine voltage waveform can be observed when monitored across CE0 and SE0 (VCE0 - VSE0).

    4)

    In EIS example,

    if(lploop_cfg.LpDacCfg.DacData12Bit>lploop_cfg.LpDacCfg.DacData6Bit*64)
    lploop_cfg.LpDacCfg.DacData12Bit--;

    above lines correct the DAC output value after removing the loading effect as mentioned in datasheet:

    In AD5940_Impedance example,

    this loading effect compensation is not done as VZERO is fixed to middle scale value.

    The below lines:

    if(AppIMPCfg.BiasVolt<-1100.0f) AppIMPCfg.BiasVolt = -1100.0f + DAC12BITVOLT_1LSB;
    if(AppIMPCfg.BiasVolt> 1100.0f) AppIMPCfg.BiasVolt = 1100.0f - DAC12BITVOLT_1LSB;

    ensure that VBIAS <=2.2V.

  • Hi Akila,

    Thanks for the response. 

    Just to be clear,

    1. So I can have a relative bias that is less than zero, correct? (VBIAS < VZERO)? So going back to that example, if I wanted SE0 to have a relative bias of -100 mV, I can set VBIAS to 1.0V and VZERO to 1.1V? 

    2. If SinAmplitudeWord is not 0 (that is, if I have a set amplitude for the sine wave and it is active), I should see VBIAS if I look at CE0-SE0? Or is it VBIAS - VZERO? If it's VBIAS - VZERO, is that the same DC bias that SE0 is then experiencing? Because I verify it using the VBIAS and VZERO PINS, but can't seem to get similar results when looking at SE0. 

    3. Is Voltage of SE0 with respect to ground = VZERO still valid if SinAmplitudeWord is not 0? 

  • Hi,

    1)

    VBias can be less than Vzero.

     To get VBias - Vzero = -100mV,

    set AppIMPCfg.BiasVolt = -100.0f

    2)

    VCE0 -VSE0 = VBIAS -VZERO

    3) Since in the above impedance example, SE0 is connected to input of TIA, and other input f TIA is connected to VZERO,

    voltage at SE0 w.r.t. GND is always VZERO irrespective of value of SinAmplitudeWord.

  • Hi Akila, 

    I set Vbias to 100 mV, and I measure that the VSEO w.r.t VCEO is -100 mV. This is correct?

    Even though I'm measuring -100 mV for VSEO - VCEO (VZERO - VBIAS), does this mean that the SE0 voltage is still experiencing a positive voltage of +100 mV?  Because if VSE0 is the working electrode and is set as VZERO, doesn't that mean that in the case of VBIAS = 100 mV, the reference (VBIAS) will always have a higher potential and therefore VSE0 will experience -100 mV?  

    So, if I want the working electrode (VSE0) to experience a bias of +100 mV, doesn't that mean VBIAS needs to be -100 mV so that VSE0 relative to the RE0 and CE0 will be +100 mV? Is there any way to turn on the DC bias first before sending an AC waveform through CE0? I did so by turning off the WG before I initialized everything else, delayed to a set time and then turned the WG on. This seemed to work to look at solely the DC bias without a superimposed waveform, but wanted to ask if there was a proper way to look at it that I was missing.

    For reference, here's how I have it set up in code: 

    HsLoopCfg.SWMatCfg.Dswitch = SWD_CE0;       // Connects WG to CE0
      HsLoopCfg.SWMatCfg.Pswitch = SWP_RE0;       // Connects positive input to RE0
      HsLoopCfg.SWMatCfg.Nswitch = SWN_SE0;       // Connects negative input to SE0
      HsLoopCfg.SWMatCfg.Tswitch = SWT_SE0LOAD | SWT_TRTIA;   // Connects SEO to HSTIA via SE0Load
    // Everything but the WG is turned on
          AD5940_AFECtrlS(AFECTRL_WG, bFALSE);
          AD5940_AFECtrlS(AFECTRL_HSTIAPWR|AFECTRL_INAMPPWR|AFECTRL_EXTBUFPWR|\
                            AFECTRL_DACREFPWR|AFECTRL_HSDACPWR|\
                            AFECTRL_SINC2NOTCH, bTRUE);
        delay (X ) 
          AD5940_AFECtrlS(AFECTRL_WG, bTRUE);
    And to measure it, I tie RE0 and CE0 together and measure SE0 w.r.t to (RE0 and CE0 together). Is this the correct method?
  • Hi,

    Yes. If Vbias is set to 100 mV, VSEO w.r.t VCEO is -100 mV.

    If SE0 is connected to input of TIA, and other input of TIA is connected to VZERO,

    voltage at SE0 w.r.t. GND is always VZERO.

    VCE0 = VZERO + 100mV.

    VSE0 = VZERO

    Yes. You may turn of WG if only DC bias is to be applied.

    You may measure the DC bias output by measuring voltage across CE0 and SE0.

    RE0 need not be tied to CE0 for this measurement.

  • Hi, 

    I disagree with RE0 not being tied to CE0. I find that for a default 1.1V measurement, CE0 measures 1.45V and RE0 measures 0.45 V. Tying CE0 and RE0 together gets 1.1V, and measuring SE0 w.r.t CE0&RE0 gets you a bias voltage of 0.0 (as expected). I'm not sure if that's intended but that's the result I've gotten across multiple breakout boards and sensors.  

  • Following up on this: I verified that the 2.5V, 1.8V references are valid. The electrode setup is the same as the previous comments. I've also attached other lines of code for reference in how I do the bias: 

        aferef_cfg.LpBandgapEn = bTRUE;
        aferef_cfg.LpRefBufEn = bTRUE;
    HsLoopCfg.HsTiaCfg.HstiaBias = HSTIABIAS_VZERO0;
    HsLoopCfg.SWMatCfg.Dswitch = SWD_CE0;       // Connects WG to CE0
      HsLoopCfg.SWMatCfg.Pswitch = SWP_RE0;       // Connects positive input to RE0
      HsLoopCfg.SWMatCfg.Nswitch = SWN_SE0;       // Connects negative input to SE0
      HsLoopCfg.SWMatCfg.Tswitch = SWT_SE0LOAD | SWT_TRTIA;   // Connects SEO to HSTIA via SE0Load
     LPDACCfg_Type lpdac_cfg;
       
        lpdac_cfg.LpdacSel = LPDAC0;
        lpdac_cfg.LpDacVbiasMux = LPDACVBIAS_12BIT; /* Use Vbias to tune BiasVolt. */
        lpdac_cfg.LpDacVzeroMux = LPDACVZERO_6BIT;  /* Vbias-Vzero = BiasVolt */

        // Uses 2v5 as a reference, can set to AVDD
        lpdac_cfg.LpDacRef = LPDACREF_2P5;
        lpdac_cfg.LpDacSrc = LPDACSRC_MMR;      /* Use MMR data, we use LPDAC to generate bias voltage for LPTIA - the Vzero */
        lpdac_cfg.PowerEn = bTRUE;              /* Power up LPDAC */
    lpdac_cfg.DacData6Bit = (uint32_t)((zeroVolt-200)/DAC6BITVOLT_1LSB);
          lpdac_cfg.DacData12Bit = (int32_t)((biasVolt)/DAC12BITVOLT_1LSB) + (lpdac_cfg.DacData6Bit * 64);
          if(lpdac_cfg.DacData12Bit < lpdac_cfg.DacData6Bit * 64) lpdac_cfg.DacData12Bit--; // compensation as per datasheet
    AD5940_AFECtrlS(AFECTRL_HSTIAPWR|AFECTRL_INAMPPWR|AFECTRL_EXTBUFPWR|\
                      AFECTRL_WG|AFECTRL_DACREFPWR|AFECTRL_HSDACPWR|\
                      AFECTRL_SINC2NOTCH|AFECTRL_DCBUFPWR, bTRUE);
    It's worth noting that I get the appropriate Vzero for the Working electrode (WE), but only the appropriate Vzero for RE if it's tied to CE. It's a three electrode system, but how come it's acting like a two-electrode setup?
  • Hi  ,

    I've responded to your other post regarding CE, RE, and SE connections.

    regards,

    Mark

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