AD7476
Production
The AD7476/AD7477/AD7478 are, respectively, 12-bit, 10-bit, and 8-bit, high speed, low power, successive approximation ADCs. The parts operate from a single...
Datasheet
AD7476 on Analog.com
I have a question about the code for reading data from the AD7476. There is a project at this ( https://opencores.org/projects/spiadc) link that has the function of continuously reading data from the AD7476.
That is, CS does not rise between conversion and at the same time the next transformation begins, as shown in the photo (nSS is CS). I did not find an exact definition of such function in the AD7476 specification. But description in opencore links says -"ability continued sequence mode - without frame entry/completing ".
Will it work in hardware? Or is it necessary making CS high between conversions?

Hello millerd,
the datasheet says: "The input signal is sampled on the falling edge of CS and the conversion is initiated at this point." and "On the sixteenth SCLK falling edge, the SDATA line will go back into three-state."
So you have to toggle CS, otherwise you won't get new conversion results.
best regards
Achim