LTC2500-32 Unable to get DRL Signal

Hi RonaldVic ,

We'll look into this and get back to you.

Regards,
Jo

Hi RonaldVic ,

Thank you for your patience. This is just an initial assessment. Are you getting an output when 32-bit was used? Since if you are not getting a busy signal, it does mean that the device is not converting.

Regards,
Jo

We are getting the BUSY signal. When using the serial port B (24 bit differential + 7 bit common mode + 1 overrange bit) we are getting the BUSY signal and we get the output. However, when trying to use the serial port A (32 bit configuration) we are not getting the DRL signal. We are getting some random output. I have attached a screenshot below of the signaltap results when using the serial port B configuration. We get the BUSY signal and we get the output as well. 

Hello RonaldVic ,

Just a clarification based on your snapshot, does the pin from your scope connected to the SDOA? So, once it is connected to this pinout, you are getting random outputs? Did I get that correctly?

Thanks and regards,
Jo

I would also like to add here, RonaldVic , to try checking this section. It is stated that RDLA should be grounded to be able to get proper output.

Can you also check your output data rate and try lowering your Vref below 5.1V? Let me know what would be the result. 

Hi Nathan,

Thank you for your response!

Yes. You got that correct. We haven't connected the scope to the board yet. We are testing the design on Signal Tap. These are the results from Signal Tap. When using the serial port A configuration, no DRL signal and random outputs from SDOA. However, when running on serial port B configuration, we get BUSY signal and SDOB gives close to expected output.

Hi Nathan,

Thank you so much for the valuable input. Below is the screenshot of the measurements from the SDOB output when providing 10V DC input. We are currently using the DC2390 board which has LTC2500 because of which we are able to provide 10V input. Unfortunately, there is no option to provide less than 5.1 V reference voltage to the ADC on the DC2390 board. Kindly let me know if it is otherwise.

Thank you & Regards

Hello RonaldVic ,

Thank you for your patience. We just got back from our holidays. Regarding your concern, here are some of my insights:

1) Have you tried this section? (Digital Interface)

2) For the DRL and Busy signal, the BUSY will go high every conversion, independently if they are using interface A or B. Meanwhile, DRL will only go high if interface A is enabled (RDLA =0) and only after it has been filtered which means, that if they are using a DF =4 (decimation factor) it will go high after 4 conversion; on the other hand, if DF=1024, it will go high after 1024 conversions.

Regards,
Jo

Hello Nathan,

I hope you had good holidays! Thank you for your response!

I have RDLA = RDLB =0. I am trying to make the design work in the averaging filter mode. Thus providing C[3:0] = 0111 and C[7:4] = DF = 0100. The final control word being 000000100111. At every SCKA, 1 bit from the control word is shifted to SDI.

The DRL signal isn't still showing up. Kindly let me know if I understood this correctly and if I am providing the correct input. 

Regards

Hi Nathan,

I was able to get the DRL signal on the board. I was making some mistake in sending the control word correctly. I was able to get the DRL signal and we are getting the 32 bit output.

How accurate can I expect the output to be? Can you suggest ways in which I can calculate the errors in the output data?

Thanks in advance for your assistance.

Regards