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Category: Software

Hi Team,

We are using AD7606C-16 for one of our current projects. We feed a constant sine wave from the signal generator 27KHz to the ADC. My sampling frequency is 108KHz (CONVST input). When we read back the ADC data & plotted on HSDC (TI Tool), we saw variations in the amplitude of the sine wave (mVpp) at certain points. Please check and suggest on this.

• Hello,

what you observe is a normal sampling effect. With your choice of signal frequency and sampling frequency you have only 4 samples per period of the sine wave.  With only 4 samples per period, your eyes do not recognize the complete curve of the sinewave.

Sometimes your 4 sampling points hit the sine wave by chance at the maximum and the minimum (and two sampling points are at the zero crossing):

An at some other times the 4 sampling points don't hit the extrema of the sinewave but are located symmetrical to the extrema:

You interprete this as a reduced amplitude of the sine wave. But as you can see in the plot it is still a sinewave with the same amplitude, but the few sampling points hit the sinewave at different positions.

best regards

Achim

• Hi Achim,

Could you please brief me a little more on this?

I understood the first scenario, but for the second scenario what could be the reasons for the 4 sampling points not hitting the extremes?
My source is constant and I am sampling at a constant freq (internal), so we should expect that the 4 sampling points should be constant for every cycle, isn't it?

Is this anything we can improve on this, I am not sure, what you say.

• Hello

I understood the first scenario, but for the second scenario what could be the reasons for the 4 sampling points not hitting the extremes?

why should the sampling just hit the extremes? Why should this be more likely than the second scenario?

My source is constant and I am sampling at a constant freq (internal), so we should expect that the 4 sampling points should be constant for every cycle, isn't it?

if the two frequencies would be exactly 27 MHz and 108 MHz, the 4 sampling points would stay constant over time. But your two frequencies are derived from different clock source (the quartz of your function generator and the quartz of  your ADC-controller). The frequencies have nominally exaclty a factor of 4, but the real factor will always have some slight deviation from this exact value. There are no two quartzes that oscilate on exactly the same frequency unless you actively synchronize both quartzes.

You can avoid the effect, if you synchronize your waveform generation and your ADC-Sampling with each other. 2 possible ways to do this would be

- derive the clock of your ADC-sampling from the clock of your waveform generation (many function generators provide their internal timing base as an output on the backside).

- trigger the ADC-sampling on the waveform (e.g. take e.g. the first sampling point in one period always when the positive zero crossing is detected). Most function generators provide a synch-output which can be used for easy triggering.

Is this anything we can improve on this

I don't see any reason to improve something. What you see is normal sampling with 4 points per signal period. Bot sampling scenarios describe the measured sine wave equally well, 4 points just do not  show the complete curve of the sine. Everything in your measurement is ok, just your expectation what 4 points per period can show is too high.

best regards

Achim

• Hi Achim,

We have the samples in FFT the peak shows the center freq.

If anything more I need I will revert to this, Thanks.

• Hi  ,

Can you help advise on this?

Thanks,
Janine

•  Hi,

Can you send your schematic? Also, may I know what board did you used in evaluating the device?

Regards,
Jo

• Hi Nathan,
I am attaching the AD7606C-16 design for our board. This is a board designed by us. The digital controls for the ADC are from FPGA.
PDF

• Hi,

Based on your schematic design, we have noticed that the digital line of your design is the same as our reference design which is good but have you checked the link/jumper position of the eval board design? you can check these default positions in our user guide provided in the link below.

Regards,

Andrei