Category: Hardware
Hello,
We are currently working on the ADC on the DC2390 board along with DE10 FPGA. We have implemented the ADC, and while we can obtain an output, it appears to be less accurate than anticipated.
I have attached a document containing SignalTap results, along with the output readings corresponding to the inputs. Everything seems to be in order; however, we suspect that the SDC (Synopsys Design Constraints) file might be a potential source of the accuracy issue. For your convenience, the SDC file is also included.
Could you kindly review the attached documents and advise if the SDC file may be contributing to the inaccurate output?
Thank you for your help and consideration in advance!
Regards
DOCX
DOCX
## Generated SDC file "DE10STD_DC2390.sdc"
## Copyright (C) 2017 Intel Corporation. All rights reserved.
## Your use of Intel Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Intel Program License
## Subscription Agreement, the Intel Quartus Prime License Agreement,
## the Intel FPGA IP License Agreement, or other applicable license
## agreement, including, without limitation, that your use is for
## the sole purpose of programming logic devices manufactured by
## Intel and sold by Intel or its authorized distributors. Please
## refer to the applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus Prime"
## VERSION "Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition"
## DATE "Thu Apr 06 18:03:59 2023"
##
## DEVICE "5CSXFC6D6F31C6"
##
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit us -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {altera_reserved_tck} -period 33.333 -waveform { 0.000 16.666 } [get_ports {altera_reserved_tck}]
create_clock -name {CLOCK_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {CLOCK_50}]
create_clock -name {FPGA_CLK1} -period 40 -waveform {0.000 20.000} [get_ports {FPGA_CLK1}]
create_clock -name {DC2390_ADC:i_DC2390_ADC|sclk} -period 20.000 [get_registers {DC2390_ADC:i_DC2390_ADC|sclk}]
create_clock -name {DAC_TOP:i_DAC_TOP|clock_divider2[2]} -period 20.000 [get_registers {DAC_TOP:i_DAC_TOP|clock_divider2[2]}]
create_clock -name {DAC_TOP:i_DAC_TOP|clock_divider[1]} -period 20.000 [get_registers {DAC_TOP:i_DAC_TOP|clock_divider[1]}]
#**************************************************************
# Create Generated Clock
#**************************************************************
derive_pll_clocks
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK1}] -rise_to [get_clocks {FPGA_CLK1}] -setup 0.170
#set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK1}] -rise_to [get_clocks {FPGA_CLK1}] -hold 0.060
#set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK1}] -fall_to [get_clocks {FPGA_CLK1}] -setup 0.170
#set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK1}] -fall_to [get_clocks {FPGA_CLK1}] -hold 0.060
#set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK1}] -rise_to [get_clocks {CLOCK_50}] 0.190
#set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK1}] -fall_to [get_clocks {CLOCK_50}] 0.190
#set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK1}] -rise_to [get_clocks {FPGA_CLK1}] -setup 0.170
#set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK1}] -rise_to [get_clocks {FPGA_CLK1}] -hold 0.060
#set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK1}] -fall_to [get_clocks {FPGA_CLK1}] -setup 0.170
#set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK1}] -fall_to [get_clocks {FPGA_CLK1}] -hold 0.060
#set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK1}] -rise_to [get_clocks {CLOCK_50}] 0.190
#set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK1}] -fall_to [get_clocks {CLOCK_50}] 0.190
#set_clock_uncertainty -rise_from [get_clocks {CLOCK_50}] -rise_to [get_clocks {FPGA_CLK1}] 0.190
#set_clock_uncertainty -rise_from [get_clocks {CLOCK_50}] -fall_to [get_clocks {FPGA_CLK1}] 0.190
#set_clock_uncertainty -rise_from [get_clocks {CLOCK_50}] -rise_to [get_clocks {CLOCK_50}] -setup 0.080
#set_clock_uncertainty -rise_from [get_clocks {CLOCK_50}] -rise_to [get_clocks {CLOCK_50}] -hold 0.060
#set_clock_uncertainty -rise_from [get_clocks {CLOCK_50}] -fall_to [get_clocks {CLOCK_50}] -setup 0.080
#set_clock_uncertainty -rise_from [get_clocks {CLOCK_50}] -fall_to [get_clocks {CLOCK_50}] -hold 0.060
#set_clock_uncertainty -fall_from [get_clocks {CLOCK_50}] -rise_to [get_clocks {FPGA_CLK1}] 0.190
#set_clock_uncertainty -fall_from [get_clocks {CLOCK_50}] -fall_to [get_clocks {FPGA_CLK1}] 0.190
#set_clock_uncertainty -fall_from [get_clocks {CLOCK_50}] -rise_to [get_clocks {CLOCK_50}] -setup 0.080
#set_clock_uncertainty -fall_from [get_clocks {CLOCK_50}] -rise_to [get_clocks {CLOCK_50}] -hold 0.060
#set_clock_uncertainty -fall_from [get_clocks {CLOCK_50}] -fall_to [get_clocks {CLOCK_50}] -setup 0.080
#set_clock_uncertainty -fall_from [get_clocks {CLOCK_50}] -fall_to [get_clocks {CLOCK_50}] -hold 0.060
#set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -setup 0.310
#set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -hold 0.270
#set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -setup 0.310
#set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -hold 0.270
#set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -setup 0.310
#set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -hold 0.270
#set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -setup 0.310
#set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -hold 0.270
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 2.000 [get_ports {CLOCK_50}]
set_input_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 2.000 [get_ports {FPGA_CLK1}]
#set_input_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 2.000 [get_ports {FPGA_CLK2}]
set_input_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 2.000 [get_ports {KEY}]
set_input_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 2.000 [get_ports {BUSY}]
set_input_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 2.000 [get_ports {SDOB}]
set_input_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 2.000 [get_ports {altera_reserved_tck}]
set_input_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 2.000 [get_ports {altera_reserved_tdi}]
set_input_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 2.000 [get_ports {altera_reserved_tms}]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {CLK_SYNC}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {SCKB}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {MCLK}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {DAC_DA[0]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {DAC_DA[1]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {DAC_DA[2]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {DAC_DA[3]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {DAC_DA[4]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {DAC_DA[5]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {DAC_DA[6]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {DAC_DA[7]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {DAC_DA[8]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {DAC_DA[9]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {DAC_DA[10]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {DAC_DA[11]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {DAC_DA[12]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {DAC_DA[13]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {DAC_DA[14]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {DAC_DA[15]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[0]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[1]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[2]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[3]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[4]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[5]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[6]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[7]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[8]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[9]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[10]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[11]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[12]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[13]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[14]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[15]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[16]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[17]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[18]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[19]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[20]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[21]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[22]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[23]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[24]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[25]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[26]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[27]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[28]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[29]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[30]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {adc_data24b[31]}]
set_output_delay -add_delay -clock [get_clocks {altera_reserved_tck}] 1.000 [get_ports {altera_reserved_tdo}]
#**************************************************************
# Set Clock Groups
#**************************************************************
set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
#**************************************************************
# Set False Path
#**************************************************************
#**************************************************************
# Set Multicycle Path
#**************************************************************
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************
