I have been messing with the duty cycle mode on the AD4130-8 and it seems like a cool feature but I do not fully understand it.
My current setup is this: I have only 1 channel enabled, CHANNEL_0 with positive input select and negative input select at AIN0 and AIN1I respectively. FIFO is enabled in watermark mode, watermark interrupt enabled and watermark value is 0x80 (128 samples/trigger when half full).
I would assume then that if my ODR is currently at 2400 SPS (by setting the FS_n bits of Filter_n register to 0x01), then after enabling duty cycle mode in the default 1/4 duty cycle, then ODR (output data rate) would be about 2400/4 = 600SPS. But this is not the case and I see a much smaller ODR of around 200SPS and I don't quite understand why this is happening. I tested this by timing how long it takes to fill the FIFO for the interrupt to generate. So I want to ask, how does the duty cycle mode affect the ODR? Is there something else going on I'm not understanding?
Thank you for your help Rod :)
[edited by: nealmcbealthenavyseal at 12:11 AM (GMT -5) on 7 Dec 2023]