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AD4130-8 Duty Cycle Mode effect on ODR

Category: Hardware
Product Number: AD4130-8

Hi,

I have been messing with the duty cycle mode on the AD4130-8  and it seems like a cool feature but I do not fully understand it.

My current setup is this: I have only 1 channel enabled, CHANNEL_0 with positive input select and negative input select at AIN0 and AIN1I respectively. FIFO is enabled in watermark mode, watermark interrupt enabled and watermark value is 0x80 (128 samples/trigger when half full).

I would assume then that if my ODR is currently at 2400 SPS (by setting the FS_n bits of Filter_n register to 0x01), then after enabling duty cycle mode in the default 1/4 duty cycle, then ODR (output data rate) would be about 2400/4 = 600SPS. But this is not the case and I see a much smaller ODR of around 200SPS and I don't quite understand why this is happening. I tested this by timing how long it takes to fill the FIFO for the interrupt to generate. So I want to ask, how does the duty cycle mode affect the ODR? Is there something else going on I'm not understanding?

Thank you for your help Rod :)



typo
[edited by: nealmcbealthenavyseal at 12:11 AM (GMT -5) on 7 Dec 2023]

Top Replies

  • Hi  ,

    You are correct, for an ODR set to 2400SPS, you can expect at effective ODR of 600SPS for 1/4 duty cycling mode. You may refer to the figure below which shows the AD4130 Sequencer Timing Diagram configured on 1/4 Duty Cycling Mode, with single channel enabled, FS=1 (ODR=2400SPS), and in watermark mode with value set to 128 samples.

    A 1/4 duty cycling mode means that the device is active for 1/4 of the time. It can be observed that the active time for 1/4 duty cycling mode is1.667ms, which is also equal to 600SPS. 

    You can also explore the AD4130 configuration using the ACE Software (software used above) which can be downloaded here: Analysis | Control | Evaluation (ACE) Software | Design Center | Analog Devices and install the AD4130-8 ACE Plugin so that you can explore the device's noise performance, frequency response, sequencer timing, and etc. without having to buy the evaluation board. You can use this software to observe the sequencer timing diagram based on the different configuration settings you will set.

    I am not quite sure why you are reading 200SPS for your setup. Can you share your register configuration for this? 

    Thanks and regards,

    Rod

  • Hi Rod,

    In my oscilloscope I see the FIFO ready interrupt being fired every ~636ms which corresponds to an effective ODR of 201 SPS. Sure, here is my register configuration:

        Oscilloscope showing when INT pin fires

    All the other registers are left at their default value. I unfortunately don't have a windows machine but I will try to download the ACE software on a friend's machine and see what I can see.

    Thanks for the help!

  • Hi  ,

    When the FIFO is enabled, the data ready signal becomes a FIFO ready signal that refers to the FIFO being ready to be read (low) or busy while being accessed by the device (high).

    In your case, the ~200SPS you are seeing is also the data ready signal of the device. I have attached a figure using the ACE software with the configuration above, but I added another cycle so that we can observe the pluses of the RDY. It is being fired every 5.417ms corresponding to ~184SPS, which you are seeing. 

    The ~200SPS you are seeing is correct, it is the your standby time + active time as observed on the figure below.

    The 600SPS effective ODR that you are expecting is just the active time, 1.667ms, corresponding to ~600SPS. It consists of the settling time + ideal conversion time (see formula below from the datasheet).

    The actual output data rate at which the data is ready to be read is the ~200SPS, which is observed from the pulses of RDY. 

    Thanks and regards,

    Rod