SPI input impedance (on SClk and Din) when powered down

Question

Hello, 
 I'll be using the AD7490 on a shared SPI bus. Some of the SPI devices on the bus, including the AD7490 could be individually powered down. Will the SClk and Din pins be safely high impedance when Vdd is 0V? 
 Dout will have a tri-state buffer on it that enabled the output when the CS line is low. 
 Perhaps there are ESD protection diodes on these inputs that will then clamp SClk and Din to ground ? 
 Thanks for the help, 
 Adam

NathanT · Accepted Answer

Hi AdamG , 
 
 Typically, ESD diodes are configured to the analog input of the ADC. Also, based on my understanding on your question, do you mean that you have powered up the Vdrive since you are pertaining to the digital lines? Please refer to the section attached below. It is stated that if the digital lines is initiated first before Vdd, as long as it is below 0.3V, the digital lines would not latch up. 
 
 We recommend powering up the device properly to initialize all lines properly. 
 May we also know what is your specific application? Since you are focused on the digital lines so that we could further assist you. 
 Regards, Jo)

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SPI input impedance (on SClk and Din) when powered down