AD4111 register write read issue.

Hi Apaul ,

In your register settings, in Interface Mode, I see that you are using continuous read mode. In continuous read mode, the only serial interface operations possible are reads from the data register. You must exit continuous read mode first, before you could read and write to other registers. To exit continuous read mode, issue a dummy read of the ADC data register command (0x44) while /RDY output is low, Alternatively, apply a software reset (that is, 64 SCLs with /CS = 0 and DIN = 1) to reset the ADC and all register contents. The dummy read and the software reset are the only commands that the interface recognizes after it is placed in continuous read mode. 

Regards,

JC

Hi JCCillion ,

I have updated interface mode register from continuous read mode to single read mode i.e. 0x0040. After that I am reading status register for ready flag instead of that I am receiving ADC error flag in status register.

I need to read 4 voltage and 4 input channel and 2 more AD4111 IC connected on same SPI with different CS signal.

hii Apaul  Can you share the basic communication code that you have developed to communicate with ad4111? Actually I problems with understanding the command sequence to initialize ad4111 and reading channels single ended. your help would work a lot for me.

Regards,

Mayur

Hi JCCillion ,

I am applying 0V, 3.3V, and 1.58V on the input.

The AVDD pin connected to 3.3V and AVSS connected to Ground.

Hi mayur09 ,

 Hi Apaul ,

Is the 1.58V the differential voltage in VIN0 and VINCOM? Is VINCOM connected to ground? Your voltage supplies and voltage inputs are within specifications so this should not flag the ADC_ERROR bit. Have you confirmed that your supply is really 3.3V by probing AVDD pin? As additional test for debugging, could you try enabling internal reference in the ADC Mode Register and use internal reference in the SETUPCON Register then try to read data? To see if the error occurs when using AVDD-AVSS as reference.

Regards,

JC

Hi JCCillion ,

The differential voltage is 2.014V between VIN0 and VINCOM, Yes VINCOM connected to ground, Yes the AVDD have 3.3V supply.

I have also updated SETUPCON register to 0x0320 and ADC mode register updated to modified clock select, adc single conversion mode and continuous conversion mode, enable internal reference. 

Now I'm not receiving adc error in status neither ready bit get low so data can not read and if I read the data register then I get 0x000000.

Hi  Apaul ,

Did you mean that you enabled Single Cycle Mode in ADC Mode register and not Single Conversion Mode? I got a bit confused. Are you pulling /CS low? 

Regards,

JC 

Hi JCCillion ,

Yes I'm pulling CS low, I have set the data conversion in adc mode to continuous and in interface mode register it is set to single read mode. Following are the register value which I'm using:

ADC Mode register = 0x800C, Interface mode register = 0x0040, channel0_select register = 0x8010, setup0 register = 0x0x0320 and filter0 setup = 0x0D00.

The status register ready flag still high and if I read data register then I get 0x69B661 at VIN0 voltage 0.00V and 2.014V.

Hi Apaul ,

Your register settings looks good to me. You should not attempt to read the data register when RDY is still high otherwise you will get incorrect results. How long are you polling RDY? Since you have enabled the enhanced filters and set it to 20SPS, the data should be readily available every 50ms. If you could share a scope shot of your SPI transactions it could help us better understand the issue. I am thinking that this maybe an SPI issue as all the registers are okay. On another note, you have set EXTERNAL CLK in the ADC Mode register. What is the frequency of your clock?

Regards,

JC

Hi,

Have you resolved your issue? If yes, I would be closing this thread.

Regards,

JC

I will be closing this thread now. If you have further questions, please feel to post a new thread.

Regards,

JC

I will be closing this thread now. If you have further questions, please feel to post a new thread.

Regards,

JC