I am trying to understand how the setting of the FIFO data threshold works. The AD4130-8 datasheet says that the threshold values for the FIFO data threshold interrupt can be specified in the THRES_HIGH_VAL and THRES_LOW_VAL bitfields in the FIFO_THRESHOLD register. However each of the bitfields (THRES_HIGH_VAL and THRES_LOW_VAL) consists only of 12 bits while the ADC samples at 24 bits. So are the bits in this FIFO_THRESHOLD register only representative of the most significant 12 bits of the threshold value and the lower 12 bits are assumed to be all 1s? Or maybe I'm just misunderstanding something. Any help would be greatly appreciated.
Thank you in advance :)
Changed the product in the title from "AD-4130" to "AD4130"
[edited by: JEstayo at 2:11 AM (GMT -5) on 14 Dec 2023]