LTC2500-32 evaluation board（DC2222A-A) +DC890B(Pscope)

Hi ogura.isao@sankyosha.co.jp ,

Yes. You are right. Given that the condition in the table is met, then the max output data rate is .25Msps (200 ksps) if your max input is 45 Mhz.

Regarding your concern on 18 MHz input, since it way below the max input frequency, then you do not have to worry about its output data rate since it is within the range of the max input frequency.

Let me know if you still have clarifications with this. So that I could further assist you.

Regards,
Jo

Hi ogura.isao@sankyosha.co.jp ,

For your second question, I cannot say that is correct. We cannot guarantee that for 18Mhz CLK IN, there will be a 0.1 MPs Output Data Rate. The relationship between CLK IN (J1) and the Output Data Rate was specified in Table 1. Please use Table 1 as a guide for the appropriate clock frequency. These are verified data.

But if you need that information for a certain application, I suggest reviewing the device's datasheet, in the application information section, on pages 31-33. The output data rate was specified corresponds to the Down Sampling Factor, (DF), Filter Type, and other parameters. 

If there is still vague on replies, let us know. Thank you.

Regards,

Red

I asked my questions because I don't know the relationship between CLK IN(J1) frequency and MCLK frequency.

And I like to apply 18MHz clock to CLK IN(J1).

so, I just like to know the PSCOPE settings to collect data.

I think Fsample is equal to MCLK frequency.

what is MCLK frequency when I use 18MHz CLK IN and

what is ODR setting in PSCOPE  for the default settings and SINC1 fliter setting?

Hi ogura.isao@sankyosha.co.jp ,

Since your input is below on the stated MAX CLK IN FREQ, you may expect a lower MAX OUTPUT CLK.  You could use the setting for the example you use in J1(CLK IN) 70MHz with 173ksps Max Output Data Rate, then take the PSCOPE readout. 

Please share with us the scope shots of your result.

The LTC2500-32 offers seven digital filter type, these are sinc1, sinc2, sinc3, sinc4, spread-sinc (ssinc), flat passband and averaging as shown in Figure 26. The output of the selected digital filter type is multiplexed into a down-sampler with a programmable down-sampling.

The configurability of the digital filter type and down-sampling rates offered in the LTC2500-32 allows the frequency response, filter settling time and output data rate to be tailored to the application.

The ratio of clock frequency to conversion rate is shown in Table 1.A rising edge on MCLK will power up the LTC2500-32 and start a conversion- this is not the same with the sampling frequency.

Thank you.

Regards,

Red

Hi,

The maximum Msps is the Maximum frequency divided by the multiplication fo DFand divider.

Example: DF=4, Divider=100 and MAX CLK IN =70MHz then MAX output rate=175ksps=70MHz/(4*100)

Regards

Joan

Who chooses  the divider value?

Is the divider value is choosen in FPGA dependent with MODE, OUTPUT and filter settings?

Is it fixed value?

Hello,

The value is fixed (the specified in the table) and depend on the mode selected.

Regards

Joan