AD7293 EVAL BOARD

Hi DenG2 ,

I am working on your request, please give me some time to evaluate the scenario you have outlined. 

Regards,

Arnost

Hi DenG2 ,

let's split answers into "two threads".

1. I have been working with the on board FETs(on daughter board) for the closed loop and... (Query raised)

Concerning your first question, I was looking at the description of the challenge you have encountered.

What comes to my mind is following Engineering Zone query (for reference :  AD7293 PAVDD Issue ). 

I believe you should consider the same, when enabling higher voltages. And add Rfilter resistor to eval. board.

Let me copy the snippet of the answer from the mentioned EZ thread  AD7293 PAVDD Issue . 

"

Could there have been a brief spike across the RSENSE when enabling the 50 V?

There are internal back-to-back diodes between RS+ and RS- for ESD protection. The diodes are capable of passing a maximum of 30mA – keeping the differential voltage to <300mV guarantees that the safe current is not exceeded.

Note that if series resistance is added it should only be in RS- for the AD7293, and it will affect the gain of the amplifier due to the 224k input impedance.

The image below shows the 105uA supply current that flows into the RS+ pin, and the RFILTER positioned to limit the current that can flow through the back-to-back diodes and out of RS-. The key point is to never allow more than 30mA to flow through either of those diodes.

There is actually provisions on the evaluation board to add these components, you are using the capacitor footprint for the 0.33 RSENSE. 

 "

Regards,

Arnost

Hi DenG2 , 

is there any update concerning the challenge described above?

Regards,

Arnost

Hi DenG2 ,

my apologies for late reply, I was looking into your query.

2. Also, I think the board have AVSS issue. AVSS is only -4.0V.  Say I set VCLAMP1 =  1.77V with PU1 push button. So the power up gate voltage is supposed to be -3VCLAMP = -5V, but what I get is -4V, which is AVSS. The max negative voltage GATE can go is AVSS which makes sense. But why is  AVSS -4V only?  How can I get that to be ~-5V.?

I would suggest to connect external AVSS voltage to -5.2V (Slightly "below -5V")  and configure part to Bipolar DAC range: −5 V to 0 V.

This is my 2nd eval board and my first board always has the gate voltage of -2.9V on power up.  AVSS voltage was around -3.3V and what I got as power up gate voltage was -2.9V.  The IC ADP3605ARZ was also not damaged and I checked the voltage across the resistors R82 and R18, and it was -3.3V. I tried to apply external -5V, but something was drawing more current and AVSS was still -3.3V. I removed U5 and  U6 and tried again, but it didnt solve the issue. What could have gone wrong with AVSS ?

It looks that AVSS is short-circuit somewhere on the board. Negative power supply from U3 is weak and it's voltage drops with applied load.  Something malfunctioning on the board proves also, when applied external voltage -5V, that actual AVSS was "clamped" to -3.3V. First which comes to my mind, is to check polarization of D3. Unfortunately I cannot see the same issue on my setup. 

Regards,

Arnost