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AD4134 calilbration in slave SPI mode

Category: Hardware
Product Number: AD4134

Hi support team,

please answer a few questions about AD4134 calibration in slave SPI mode:

1. It is stated in a footnote that "The gain error is a function of the output data rate in slave mode." What is the typical value of this error (in ppm of FSR) for ODR in the range 1 to 100 kHz?

2. In my design, AD4134 inputs are driven by LTC6363-05 amplifiers, and those in turn are driven by OPA2182 amplifiers as (single-ended) input buffers. I connected one of the inputs to the VREF = 4.096 V (nom), and measured 2.047 V using the default AA1 filter and 40 kHz ODR. When I changed the filter to AA2, with everything else unchanged, I measured voltage was 2.045 V, the difference being about 0.1%. Therefore, the question is: do gain and/or offset errors in the slave SPI mode depend not only on the ODR, but also on the chosen filter?

3. To provide some headroom to LTC6363, I changed the OCM voltage from the default value of (10/20)*Vref to (12/20)*Vref. The measured voltage changed by about 4 mV under the same conditions as above, which is about 1 % of the OCM voltage change. CMMRO of the LTC6363 is about 80 dB. Therefore the question is: does the OCM setting really affect the AD4134 calibration, or I should review my front-end design?

4. Lastly, a general question about SPI access to the registers: can multiple registers be accessed within a single CS = 0 "frame?". In other words, can I set CS = 0, do all necessary setup for all registers, then set CS = 1, and proceed to data acquisition?  Or it is required to "frame" each accessed register with its own CS = 0 pulse? For your information, I'm using two separate SPI interfaces for the registers and for the data. 

Thanks in advance, 

Michael

Top Replies

  • Hi  ,

    Please refer to the responses below.

    1. The typical value of the gain error should be within the data sheet specifications.

    2. A small change in current can cause this offset error but this…

  • Hi  ,

    Please refer to the responses below.

    1. The typical value of the gain error should be within the data sheet specifications.

    2. A small change in current can cause this offset error but this can be fixed through calibration.

    3. The common mode voltage should not affect the calibration. Can you share your schematic so we can further check?

    4. Yes, this should be okay as long as SCLK is in multiple of 8.

    Thanks,
    Janine