AD7980 in 4-WIRE CS MODE WITHOUT BUSY INDICATOR, How many AD7980 can be conected in this way? In datasheet, the example of this application is only two parts, if possible, connected three or more?

Hi Sara123 ,

Please refer to page 21 of the datasheet. It states that the 4-WIRE CS WITHOUT BUSY INDICATOR is a configuration when using multiple AD7980. Thus, you can use 2 or more AD7980.

Regards,

Jo

Hi NathanT，

Thanks for your reply，we have tested with 3 AD7980  to an SPI-cmpatible digital host. but there are some errors. would you mind giving the right timing diagram? By testing,the SDOs connected together can not get the right results. if seperated, it is ok. So it maybe somethings wrong,  Could you give the application example?

Thanks.

Hi Sara123 ,

May I know what are the errors you are getting? And may I also know if you are getting any error if you are using only two AD7980? Or are there any confusions when using only two AD7980?


Moreover, for your reference, here are some of my insights to guide you in your concern:

1) Make sure that the digital host you are using also has three Chip Select (CS) since you have stated that you are using three AD7980. The CS of the 1st AD7980 should be held low for you to select the device. 

2) Kindly refer to page 21 of the datasheet. It states that after every falling edge of the 16th clock pulse of the SCK, SDO will be held to high impedance while the SDI of the first AD7980 should be held high. And the next AD7980 can be read by being held low. So, the third AD7980 should be held low after the 32nd clock pulse.

Let me know if this would help you so that I could further assist you. 

Regards,
Jo

Thanks for your reply.

What Sara123 said was the problem I encountered in my work. My English is not good, her help me ask.

In actual measurement, When CNV rises, all three CS are at high levels.The sck signal is present and not shown in the figure. At position 1840 of the timing chart, after the 16th falling edge of the clock, SDO1 has completed 16 bit data transmission，both SDO2 and SDO3 have signal outputs although all CS are high. I think it ould be  because SDO data is valid on both the rising and falling edges of the clock, and SDO must be output before the rising and falling edges of the clock. In this case, connecting SDO together will result in error.

Hi woodjohn ,

Is it possible to upload the higher quality of the scope shot so that we can assess or see the error better?

Regards,

Jo

this one

other 

All SDOs are connected to Pull-up resistor

All SDO connection pull-down resistors

schematic diagram

The error occurred between two SDOs of AD7980 that did not send out data in 3 AD7980 system.   If only two AD7980 chips were used in the system, this problem would not occur. There will only be one AD7980 waiting to send data.

Hi woodjohn ,

You have stated that when you are using only two AD7980, you are able to get the proper output with a proper timing diagram, as per stated in the datasheet. May I request some screenshot from your scope if your configuration is two AD9780? So that I could properly assess your concern. And so that I could further assist you.

Regards,
Jo

Hi woodjohn ,

You have stated that when you are using only two AD7980, you are able to get the proper output with a proper timing diagram, as per stated in the datasheet. May I request some screenshot from your scope if your configuration is two AD9780? So that I could properly assess your concern. And so that I could further assist you.

Regards,
Jo

We have holidays from June 22nd to June 24th and work on June 25th. I‘m glad to create some pictures of the two AD7980 systems. What kind of pictures would you like to see that are more useful. like I have sent picures?

Hi woodjohn ,

Pictures just like the one you have sent yesterday. Output of the system but just using two AD7980. So that I could properly assess your concern and so that I could further assist you.

Regards,

Jo

In 3 AD7980 systems, when AD7980A completes sending data, the SDOs of AD7980B and AD7980C will output data at the same time, which may cause conflicts. But in 2 AD7980 systems, when AD7980A completes sending data, only AD7980B is waiting. There are no problem with the 2 AD7980 systems. I don't know what I can do?

In the pictures I have sent, the control signals obtained by the 2th AD7980(AD7980B) and the 3th AD7980(AD7980C) are exactly the same, but the analog signals are different. From the above pictures , if all of the 3th AD7980(AD7980C) is deleted, it will be the pictures of the 2 AD7980,

Hi woodjohn ,

I would suggest trying the configuration given in the datasheet. Connect all SDO of the AD7980 to a single data in of the host and configure each chip select (CS) to low sequentially. Which in your case, you have multiple data in for each SDO of AD7980. 

Let me know if this helped you in your concern so that I could further assist you. 

Regards,
Jo

I used the configuration provided in the datasheet first, just like the graph you provided, but it made an error and could not read back the correct AD conversion value. I suspect that 3 AD7980s cannot be used in this mode. In order to analyze the reasons, I separated the SDOs. Only SDOs is separated, everything else is the same. If there are no conflicts between the separated SDOs, they can be connected together. But I observed a conflict. The previous image shows the details of the observed conflict.

After separating the SDOs, I can read the correct AD conversion values. But the AD7980s that I did not read simultaneously output the highest bit of AD conversion results (estimated through analog signals). In this case, if SDO is connected together, an error will occur.

笔记

Hi woodjohn ,

You can try checking your configuration for chip select (CS). Make CS1 low if you will be using the AD7980_A from your set up. Then after using the first AD7980 make its CS high, before making CS2 low for AD7980_B. And so on.

Regards,
Jo

After separating the SDOs, I can read the correct AD conversion values from any of the three AD7980s. If two AD7980s are used(SDO connected together), the correct value can also be read from either one.This figure shows the application of CS.