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AD7980 in 4-WIRE CS MODE WITHOUT BUSY INDICATOR, How many AD7980 can be conected in this way? In datasheet, the example of this application is only two parts, if possible, connected three or more?

Category: Datasheet/Specs
Product Number: AD7980

AD7980 in 4-WIRE CS MODE WITHOUT BUSY INDICATOR, How many AD7980 can be conected in this way? In datasheet, the example of this application is only two parts, if  possible,  connected  three or more?



update the issue. PN is AD7980
[edited by: Sara123 at 8:11 AM (GMT -4) on 16 Jun 2023]

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    •  Analog Employees 
    in reply to woodjohn +1 verified

    Hi  ,

    I would suggest trying the configuration given in the datasheet. Connect all SDO of the AD7980 to a single data in of the host and configure each chip select (CS) to low sequentially. Which…

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  • Hi  ,

    Please refer to page 21 of the datasheet. It states that the 4-WIRE CS WITHOUT BUSY INDICATOR is a configuration when using multiple AD7980. Thus, you can use 2 or more AD7980.

    Regards,

    Jo

  • Hi NathanT,

    Thanks for your reply,we have tested with 3 AD7980  to an SPI-cmpatible digital host. but there are some errors. would you mind giving the right timing diagram? By testing,the SDOs connected together can not get the right results. if seperated, it is ok. So it maybe somethings wrong,  Could you give the application example?

    Thanks.

  • Hi  ,

    May I know what are the errors you are getting? And may I also know if you are getting any error if you are using only two AD7980? Or are there any confusions when using only two AD7980?


    Moreover, for your reference, here are some of my insights to guide you in your concern:

    1) Make sure that the digital host you are using also has three Chip Select (CS) since you have stated that you are using three AD7980. The CS of the 1st AD7980 should be held low for you to select the device. 

    2) Kindly refer to page 21 of the datasheet. It states that after every falling edge of the 16th clock pulse of the SCK, SDO will be held to high impedance while the SDI of the first AD7980 should be held high. And the next AD7980 can be read by being held low. So, the third AD7980 should be held low after the 32nd clock pulse.



    Let me know if this would help you so that I could further assist you. 

    Regards,
    Jo

  • Thanks for your reply.

    What Sara123 said was the problem I encountered in my work. My English is not good, her help me ask.

    In actual measurement, When CNV rises, all three CS are at high levels.The sck signal is present and not shown in the figure. At position 1840 of the timing chart, after the 16th falling edge of the clock, SDO1 has completed 16 bit data transmission,both SDO2 and SDO3 have signal outputs although all CS are high. I think it ould be  because SDO data is valid on both the rising and falling edges of the clock, and SDO must be output before the rising and falling edges of the clock. In this case, connecting SDO together will result in error.

  • Hi  ,


    Is it possible to upload the higher quality of the scope shot so that we can assess or see the error better?


    Regards,

    Jo

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