Hello. We are interfacing an LTC2512-24 in an application where we do not need to run at very high speed. We don't expect to need a SCKA to go beyond 32 MHz, however, in order to sample the first bit of data after DRL goes LOW, we would like to setup the SPI bus with the CLK polarity ACTIVE LOW. That then allows us to sample on the leading (Falling) edge of the SCKA to ensure we can read the first bit BEFORE the rising edge of the clock triggers the LTC2512 to move to the next bit.
From the LTC2512-24 spec diagrams, it seems that the 'normal' configuration is to have the SCKA polarity set to ACTIVE HIGH, and unfortunately in that configuration sampling on the leading (Rising) edge of the clock isn't meeting the hold time requirement of our processor, which needs around 18ns.
Although there doesn't seem to be a clear statement that the SCKA polarity must be ACTIVE HIGH, will it work correctly with the polarity set to ACTIVE LOW ?
Thanks in advance !
