AD4134
Recommended for New Designs
The AD4134 is a quad channel, low noise, simultaneous sampling, precision analog-to-digital converter (ADC) that delivers on functionality, performance...
Datasheet
AD4134 on Analog.com
AD7134
Not Recommended for New Designs
The AD7134 is a quad channel, low noise, simultaneous sampling, precision analog-to-digital converter (ADC) that delivers on functionality, performance...
Datasheet
AD7134 on Analog.com
Dear Support Team,
I'd like to use the AD4134 ADC in the "minimum I/O" mode. Please answer the following questions:
1. On page 69 of the DS, last paragraph on the left, it is said: "On power-on, the AD4134 boots up in minimum I/O mode and a toggle on pin makes the device exit the minimum I/O mode". But the DS of AD7134 has "on the CS pin" in the same place, so I suggest making a correction to the AD4134 DS.
2. What is meant by "On power-on, the AD4134 boots up in minimum I/O mode". Does AD4134 boot in that mode regardless of the CS pin state at power-on, or CS must be a logical 0 at power-on? I'm asking because this sentence comes before the description of the detailed minimum I/O mode configuration.
3. What does it mean "a toggle on the CS pin makes the device exit the minimum I/O mode"? Exit forever (until the next power-on), or setting the CS pin back to 0 without power cycling the ADC will put it back into this mode? I noticed that some people questioned about using several ADCs in their systems, all in this minimum I/O mode, and have gotten the positive answer, if only one ADC is chosen at a given time by the corresponding CS, as if it were a regular SPI interface. But the DS phrasing "makes the device exit" without any reference to the possibility of return arises some doubt. Therefore, my question is: if the ADC is configured (wired) as shown in Fig. 122, with the only difference that CS = 1 at power-on, will it be possible to enter and exit the minimum I/O mode by manipulating the CS pin after the power-on?
4. Regarding the configuration, I assume that the ADC must be in the SPI control mode, that is, PIN/SPI = 1. Is this correct?
5. The DS says "perform the following sequence", but the steps 1 - 4 do not seem to form a "sequence" since they are normally done during layout, and therefore describe the state of the relevant pins at power-on. My understanding is that the actual sequence is: prepare the hardware configuration as listed in steps 1 - 4, power-on the ADC, configure the registers as described in steps 5 and 6. Is this correct?
6. Can the SDO_PIN_SRC_SEL bit be set and reset later if needed? If I first use the SPI interface normally, for communicating with registers, and a separate interface for reading the data, and then suddenly set the SDO_PIN_SRC_SEL bit to 1 -- what will happen?
7. After all, what does it actually mean "to be in the minimum I/O mode" and how does the ADC know if it is there? Connecting SCLK and DCLK together and forcing the data through the SDO pin does not seem to affect the SPI functionality in any way. Yet it is stated that it is impossible to disable CRC in the minimum mode, suggesting that there must be a stronger reason to do so.
8. Frankly, I would use the configuration shown in Fig. 122 even if it had not been mentioned in the DS, with the only difference of using the CS pin to choose between accessing the registers and the data. Can this be done? Will this still prevent the possibility of disabling the SPI CRC?
9. It is my understanding that the relevant timing diagrams for this mode are shown in Fig. 2 and Fig. 4. Correct?
Thanks in advance,
Michael
