AD7386 SPI interface

Hi ay0101 ,

To clarify your confusion on the datasheet, yes, it is stated that the data bits are valid on both the rising and falling edges. But based on the timing diagram, you should configure your code so that it should accept the data on the falling edge. Since the data will be shifted on the rising edge while the data will be sampled at the falling edge.

May I also know what specific application are you going to use this? Since you have mentioned about configuring your code at the rising edge. So that I could further assist you with your concern. 

Regards,
Jo

Hi Jo,

Thanks for the response. I will have my VHDL code to sample the data at the falling edge, then. But the register write part is still unclear to me, and since I will use AD7386 in 1-wire mode with Channel 1 selected, I need to be able to write to the registers before reading any conversion results. 

Another thing is, using the 1-wire mode, I will read the results in 32 clk cycles. Since the CS falling edge will trigger another conversion, do I need to wait 32 clks when writing or reading anything? Or can I just take CS to high before the conversion results are fully shifted out?

Thanks in advance. 

Hi Jo,

Thanks a lot for the information. My last question is, do I need to shift out the data I want to write on the falling edge or the rising edge? As I said before, the timing diagram and the snapshot in this post seem to be conflicting. 

Thanks.

Hi ay0101 ,

Based on your concern, you should write your data on the falling edge. (Please refer to page 10. Figure 2. Tsdis and Tsdih)


You can also refer to this link for your VHDL code:

AD738x - No-OS Driver [Analog Devices Wiki]


Regards,
Jo

Hi Jo,

Thanks for your response. I wrote to the registers as you said. First SCLK falling edge occurs 10 ns after CS goes low, and the data changes occur at the falling edges. I wrote 0x800 to register 1, and 0x100 to register 2, in order to use 1-wire mode and channels A1 and B1. Then I try to read back from registers but the data I read changes with every command, and it does not seem to make any sense. Also when I read the ADC data, I see only 16 bits of data, so I guess I cannot successfully write to registers. 

The first snapshot below shows the SDI into the device (yellow), and the CS signal (blue). The second one shows the same data but with SCLK. Sorry about the quality of the snapshots. Do you see any problem with these?

Thanks a lot,

Ayse

Hi ay0101 ,

First of all, I would like to apologize for the confusion I have made. Based on my last response, I have stated that you should write your data at the falling edge of the SCLK, just like on the 2nd photo you have given. But upon checking the timing diagram, you should start writing as the SCLK rises up until the hold time in falling edge (tsdih). Please refer to the image below.

The red line signifies where you should start writing your data. And the blue line signifies the range of maximum hold time of your data (tsdih).

On the other hand, I would like to suggest that you could also check your connections and probes of the digital lines for a better output signal. You can use the example scope shot below of good digital signal lines as your reference.

Let me know if these feedback answers your concerns, so that I could further assist you.

Regards,
Jo

Hi Jo,

I am finally able to write to registers and read ADC data successfully! Thank you for all the help :)

Ayse

Thanks for the update..

Thanks for the update..