Hello! I am trying to use the SPI interface of AD7386 but I'm confused about the timing diagram on the datasheet. It says in the datasheet that the data is shifted out of the device on the rising edge of SCLK, and the receiving part can sample both on rising/falling edges. So I designed my VHDL code to accept the data on the rising edge, is that okay? The datasheet says nothing about the timing of a register write though. The snapshot here implies that I should shift out the data I want to write to the register on the falling edge so that AD7386 can sample it on the rising edge? It could be great if anyone could state it clearly. Thanks in advance.