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ADAQ23875 missing digital output

Category: Hardware
Product Number: ADAQ23875


in the past we had done some experimentation with your ADAQ23875 eval board, all working fine.

We now have implemented our own design, connecting several ADAQ23875 to a Xilinx Kintex-7 FPGA, our own VHDL code.

We believe to have hooked up the ADAQ23875 exactly as outlined in the datasheet, employing single-lane mode.

What we observe, for all ADAQ23875 devices connected:

- on DCO we receive back the echo clock correctly

- on DA we have a constant 0, irrespective of engaging TESTMODE or supplying analog input.

We verified compliance to your datasheet thoroughly.

We inspected the eval board documentation and found one difference to the datasheet:

- eval board: pin K4 is open, NC

- datasheet: pin K4 is GROUND.

We appreciate any comments.

Thanks and best regards


Top Replies

  • Hi  ,

    Just to clarify, are you referring to the TESTPAT pin when you say TESTMODE? If I am interpreting it correctly, if you apply a HIGH (VIO) to the TESTPAT pin, you still read a constant 0 pattern instead of the 1010 0000 0111 1111 for One-lane mode? Please feel free to correct me regarding your setup.

    On the other hand, K4 pin is connected internally to the other ground pins of the device itself — meaning there is no problem if it is open/not connected in the evaluation board. 

    Few things that seem suspicious are the neighboring pins, especially the REFIN (K3) and PDB_ADC (K5), since they might be shorted to ground. 

    • If REFIN = GND: the reference buffer might have turned off, resulting to no reference voltage for the ADC core
    • If PDB_ADC = LOW: the internal ADC core might have entered to power-down mode — meaning all circuitry (including the LVDS interface) shuts down

    It would be great if you could share more information regarding your configuration. Please do message in this thread if you have further queries.

    Thanks and regards,

  • Hello Chelsea,

    you describe perfectly well what I meant to say.

    Menawhile I have resolved the problem, it was due to an error within my VHDL code.

    I am receiving testpatterns as well as ADC samples perfectly well know.

    Good to know that the K4 difference eval Board/datasheet is of no relevance.

    Thanks a lot, very best regards


  • Glad to hear that! Thanks for reaching out.


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