AD4134
Recommended for New Designs
The AD4134 is a quad channel, low noise, simultaneous sampling, precision analog-to-digital converter (ADC) that delivers on functionality, performance...
Datasheet
AD4134 on Analog.com
Hello, we are planning on using AD4134 ADC in our application and were looking for ways to wire it up to the MCU properly. A little bit about the specifications of the project:
- We have 4 physically detached modules that contain a single AD4134 ADC each
- Each module is connected to an MCU (STM32H7) board with an FPC cable
- Each ADC samples 4 channels simultaniously at a speed of 8 ksps, however only one ADC at a time. For example, we would start sampling ADC0 and read the data for 5 seconds, then stop sampling ADC0, start sampling ADC1, read for 5 seconds, stop sampling etc. until all 4 ADCs are read, then repeat.
We read through your datasheet but still have issues understanding some things. If we understand correctly, we can use a single DOUT0 for reading out all of the data, given the rather slow 8 ksps sampling speed. Even better, from the datasheet we can also see that there is a minimum I/O mode, where the configuration and data readout is done over a single SPI bus, which seems to be something that would work best for us. However, it specifies wiring pin FORMAT0/CS to GND, meaning the ADC is ALWAYS active on that SPI line. Thus the question, using this Minimum I/O mode, can we potentially control the FORMAT0/CS line by the MCU and thus control and read the data from 4 separate ADCs at the same time on the same SPI line? And again what I mean by "at the same time", is that the readouts are multiplex instead of being done simultaniously.

Hi Montye ,
We will look into this. I will contact the product owner and get back to you.
Regards,
JC
Hi Montye ,
In this minimum I/O mode, the ADC conversion data is read in the SDO pin, which can be configured in the DEVICE_CONFIG register.
You can provide dedicated chip select lines to the 4 ADCs to switch between these ADCs by toggling the chip select = low (active), and high (idle), but the DOUT of the other ADCs should be disabled.
Thanks,
Janine
I believe this is wrong, since what we learnt is that by toggling CS line the device exists the minimum I/O mode, so in practice, there is no reason to CS lines as these need to be grounded (in Minimum I/O mode) isn't that right?
Hi,
You mentioned that the 4 ADCs will share the same SPI line. If the CS of the ADCs are grounded, all ADCs are active on the SPI lines. Hence, I suggested to control which ADC will be active on the SPI line by making use of the CS of these ADCs.
In minimum I/O mode, the figure does state to ground the CS pin, as in this case, there is only one ADC connected.
I hope this clears things up. Let me know if you have any questions.
Thanks,
Janine
So what we found out is that to integrate 4 ADCs, all in Minimum I/O mode, all sharing the same SPI line, it might be best to use 4 voltage level translators (e.g. TXU0304), each with an EN pin. Then one can control which ADC is being communicated with, we can also then power-down the unused ADCs safely to reduce heat dissipation.
Although can you confirm if this would also work. If I understand correctly, one could keep all CS lines high, thus the chips are NOT in Minimum I/O mode, also all of the ADCs must be powered-up. However, before starting the communication with the desired ADC, one should pull that ADC's CS line to LOW and power-cycle (or reset might be enough?) that ADC for it to go back into Minimum I/O mode. Then communicate with it in Minimum I/O mode as desired, but after finishing pull the CS line HIGH for that ADC to leave Minimum I/O mode, and for the comms to be ignored with that ADC. Does that sound correct?
Hi Montye
Firstly, for CS lines if you desire to convert from 3.3V then you dont need level translators. Resistor dividers can work for this unidirectional line.
same goes for PDN signal as well.
Now if understand the scenario correctly,
You have wired to each ADC - CS, ODR, SCLK/DCLK, SDI, PDN1, SDO/DOUT0
CS and PDN are not common, so for ADCx you have CSx, PDNx signal. Rest 4 signals ODR, SCLK/DCLK, SDI, SDO/DOUT0 are all shared in the 4 ADC's
Please confirm
thanks