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Sample is getting junk data in SPI ADC71716_2 ADC chip .

Category: Hardware
Product Number: AD7176-2

Hi ,

I am testing the ADC7176_2 EVK board to connect with STM32H750 SPI line.

I followed the AD7176_2 driver code and configured the SPI mode 3 and communicate 16MHZ.

I can able to read product id and configure register of AD7176_2 ADC.

I used mode continue conversion mode and collect 100 sample in every sample collect 100 micro second.

I feed the 3.3 voltage and raw value approximately (0xa9ac55) . 

I am getting the 1 or 2 sample junk value from 100 sample and randomly like value (0x537610 , 0x1f7 , 0xffc000). I used single conversion mode also similar issue.

Please give any suggestion for avoid junk value from ADC chip.  

corrected product number to AD7176-2
[edited by: JCCillion at 12:43 AM (GMT -5) on 7 Feb 2023]

Top Replies

    •  Analog Employees 
    Apr 3, 2023 in reply to rajeshkannan +1 verified

    Hi  ,

    Apologies for the late response. From your scope shot, the /CS returns high after the data read. When /CS is high, the DOUT/RDY pin is tri-stated. The /CS must be low in order for DOUT…

  • Hi  - Is the end of conversion (RDY signal)  monitored before reading the data? The falling edge of the RDY signal needs to be monitored (Via an interrupt or by polling the GPIO level of the RDY signal) to ensure that the data is not being read when the conversion is happening. This monitoring needs to happen for single and continuous conversion modes. In single conversion mode, polling of the RDY bit in the status register (Address:0x00) is also an option.


    Janani Sunil.

  • Thank you for quick reply.

    Now we are polling the RDY signal and observed the RDY signal is not going to HIGH when the data LSB bit is zero (EX: 0x934d64). But when the data LSB bit is 1 (EX: 0x934d6b),RDY signal state is HIGH and after the conversion AD7176_2 is changing the RDY signal to LOW.

    Please let us know why the RDY signal stays low when the ADC data  LSB bit is 0.


    Rajesh Kannan.

  • Hi Rajesh, 

    When you stop reading the data conversion for example, and just upon power up, try to monitor the /DRDY pin when /CS is low. Is it pulsing at default output data rate? Then try to change the output data rate by writing to the appropriate register. Read back the register to ensure that the correct value was written. Again, with /CS low, check that the DOUT/RDY pin is pulsing at the new selected output data rate.

    When DOUT/RDY stops pulsing at any time and it stays high or low (even though the ADC is configured for continuous conversion mode), this indicates that the serial interface has become asynchronous (incorrect number of SCLK pulses, glitches on the SCLK line). Ensure that the correct number of SCLK pulses are being used for each read/write operation. It is also recommended to tie DIN and SCLK high when they are not being used to prevent glitches affecting the SPI interface.

    Would you be able to share a scope shot of your digital interface about the two scenarios that you have mentioned above? 


  • Hi Jellenie,

    Thanks for reply,

    After the power on with default configuration ,It is pulsing MISO(RDY) pin and data is FF(So LSB bit is always 1). By setting only Channel 0 Enable (CHMAP0 register), Data is observed and whenever LSB bit is 0 ,RDY pin low only.

    I have captured the logical analyzer for the two scenarios and uploaded the same. 

    PiC1: LSB bit is 1 and LSB bit 0 

    RDY When LSB 0 and LSB 1

    Pic 2: When LSB bit is 1 RDY is PULSING 

    When LSB bit is 1 RDY is PULSING

    Pic 3: When LSB bit is 0 RDY is LOW 

    When LSB bit is 0 RDY is LOW

    Thank You

  • Hi, 

    Apologies for the delay in coming back to you. Can you include the MOSI in this scope shot please? Can you also measure the time between your two consecutive /RDY signal and how it relates to your programmed ODR?

    This is interesting, as the DOUT/RDY pin should go high after the data word has been read from the data register, indicating that either:

    1. An insufficient number of SCLKs were provided or
    2. The AD7177 did not think this was a data read operation.

    Is it possible to keep your SCLK idle high?

    Is it also possible to pulsed /CS high between SPI operations? It could improve communications robustness. /CS = 1 resets the internal SPI logic, but not the register settings, allowing the Host and the ADC to recover synchronization if it was lost due to spurious SCLK edges in a previous transaction.


  • Thanks for the reply and sorry for the delay,

    Please find below the captured picture to observe MOSI,MISO/RDY ,CS and CLK. Also we are providing the register dump for your analysis. 

    As our requirement is 25 KSPS(25000 samples per second), so we cannot consider the single conversion mode. 

    SPI AD7176-2 MISO,MOSI,CLK and CS

    Register Dump:

    STATUS                     0x00 --> 0x0000

    ADCMODE                0x01 --> 0x2000

    IFMODE                    0x02 --> 0x0000

    GPIOCON                 0x06 --> 0x0006

    ID                              0x07 --> 0x0C94

    CHMAP0                  0x10 --> 0x8c01

    CHMAP1                  0x11 --> 0x0000

    CHMAP2                 0x12 --> 0x0000

    CHMAP3                 0x13 --> 0x0000

    SETUPCON0          0x20 --> 0x0000

    SETUPCON1          0x21 --> 0x0000

    SETUPCON2          0x22 --> 0x0000

    SETUPCON3         0x23 --> 0x0000

    FILTCON0              0x28 --> 0x0005

    FILTCON1             0x29 --> 0x0200

    FILTCON2             0x2A --> 0x0200

    FILTCON3             0x2B --> 0x0200



  • Hi  ,

    Apologies for the late response. From your scope shot, the /CS returns high after the data read. When /CS is high, the DOUT/RDY pin is tri-stated. The /CS must be low in order for DOUT/RDY to pulse. 

    Kindly try this sequence and monitor the DOUT/RDY goes high while /CS is low.

    0x44 -> pulsed /CS - read data (applied SCLKs) -> wait until DOUT/RDY goes high (/CS low)