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AD4110-1 - Max sample rate for 24 bits

Category: Datasheet/Specs
Product Number: AD4110-1
Software Version: 1.5 EVAL BOARD

I'm testing an AD4110-1 for a product and am trying to verify 24-bit performance at the maximum sample rate.

When injecting a 100 Hz sine wave with:

ADC_Config = x1301

Filter_Config = x0501

ADC_Interface_Mode = 0x0000 

ADC_Mode = 0x0000 (ADC OUTPUT 24 bits)

am expecting that a 1250 sample collection will give me one cycle at 100 Hz, sampled at 24-bits and 125 kS/s. Instead I see two cycles indicating the true sample rate is 62.5 kS/s despite what is indicated.

When I change 

ADC_Config = x1301

Filter_Config = x0501

ADC_Interface_Mode = 0x0000 

ADC_Mode = 0x0001 (ADC OUTPUT 16 bits)

I am now sampling at 16 bits, and a 1250 sample collection gives the expected one cycle, indicating a 125 kS/s cycle rate.

Does AD4110-1 only support 125 kS/s at 16 bits? I can't find that referenced in the datasheet. What am I missing?



Removed LMXMprodsupport tag.
[edited by: emassa at 4:56 PM (GMT -5) on 20 Jan 2023]

Top Replies

    •  Analog Employees 
    •  Super User 
    Jan 31, 2023 in reply to stevenwSCI +1 verified

    Hi  ,

    The AD4110 should have a 24-bit output at 125kSPS as specified in the datasheet, you can also confirm this by monitoring the /DRDY pin (/CS low) and see if this is pulsing at correct ODR…

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  • Hi JC,

    Thank you for replicating the issue.

    Can you give any detail on where the software limitation comes from? It's not a big deal since the AD4110 doesn't have >>16 ENOB at 125 kS/s, but I wanted to make sure that when I hook up a logic analyzer and implement on custom electronics that I should expect the whole 24-bit output.

    Best regards

    Steve

  • Hi  ,

    The AD4110 should have a 24-bit output at 125kSPS as specified in the datasheet, you can also confirm this by monitoring the /DRDY pin (/CS low) and see if this is pulsing at correct ODR. Then your controller/processor (if faster) should be able to read the data as 24 bits or 16 bits which can also include the status (+8bits). Our software/platform is also capable of reading this at slower rate. The limitation/issue that was mentioned above is that our software/platform might have been missing out some of the samples when the data is set at 24 bits and when using the fastest speed. This could only be an issue specific to our Eval software and SDP-B platform due to speed limitation. We are now moving to a new platform and ACE plugin. We intended to get this work correctly onto our new software/platform with faster speed. Apologies for inconvenience we will let you know once we have the available firmware/software in place.

    Regards,

    JC