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AD7768-4 /DRDY behavior

Category: Hardware
Product Number: AD7768-4

In Filter Settling Time section of the datasheet page 59,  deterministic delays until the first new conversion result is available, and until the first settled data are explained.

what is the first new conversion result? what is the actual settling time ? in the case that the channels are configured with the wideband filter and MCLK_DIV = MCLK/4,

with some channels assigned to Group A with decimate by 32 and other channels to Group B with decimate by 64 (Table28).

Are /DRDY pulses three generated  times (758, 8822, 17014) ?

What are delays from First MCLK Rise After SYNC_IN Rise to First DRDY Rise , and  Delay from First MCLK Rise After SYNC_IN Rise to Earliest Settled Data DRDY Rise when I use wideband fiter for GroupA and sinc5 filter for GroupB?

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