AD7768-4 /DRDY behavior

Hi ogura.isao@sankyosha.co.jp ,

We will look into this. I will contact the product owner and get back to you.

Regards,

JC

Hi  ogura.isao@sankyosha.co.jp 

Apologies for the delay.

The first new conversion result will be available or represented by the "Delay from the First MCLK Rise After SYNC_IN Rise to First DRDY Rise". An ADC conversion result is available at this time but the digital filter has not fully settled, thus, the result does not actually represent the state of the analog input since /SYNC_IN was released.

The “Delay from First MCLK Rise After /SYNC_IN Rise to Earliest Settled Data /DRDY Rise” is the time when the first settled data is available.

When some channels are assigned to group A with decimation factor by 32, and other channels to group B with decimation factor 64 and both using the wideband filter, AD7768 will output the first /RDY indicated by "Delay from the First MCLK Rise After SYNC_IN Rise to First DRDY Rise" which is 758 MCLKs and subsequent /DRDY pulses will be produced at the fastest ODR every 128 MCLKs (ODR equals 32*4 = 128MCLKs).

The statement below is indicated in the Channel Mode A Register section of the datasheet (page 79)

“When different decimation rates are selected, the AD7768 outputs a data ready signal at the fastest selected decimation rate. Any channel that runs at a lower output data rate is updated only at that slower rate. In between valid result data, the data for that channel is set to zero and the repeated data bit is set in the header status bits to distinguish it from a real conversion result (see the ADC Conversion Output: Header and Data section)”

When using two different filter type for Group_A and Group_B the Group with lowest decimation value (highest ODR) will determine the /DRDY pulses. If the same rate was used, then the device will prioritize sinc5 over FIR as it has a better settling time. But the key thing here is to monitor the /DRDY pin, read the conversion results + header bits, indicating if the data is repeated, and if the filter is not settled to know when is the valid conversion for a specific channel.

Thanks,

Would you tech me a little more about /DRDY signal when I set some channels are assigned to group A with decimation factor by 32, and other channels to group B with decimation factor 64 and both using the wideband filter.

You said I would observe /DRDY rise at 758MCLK.

Do I observe /DRDY rise every 128MCLK after 758MCLK and group A data is settled at 8822 MCLK which is 63th /DRDY after 128MCLK?

At that time Bit6 of Header status bits change from 1 to 0?

Hi ogura.isao@sankyosha.co.jp ,

Yes, the first /DRDY will be produced at 758 MCLKs. The digital filter result is not fully settled. Thus, the bit 6 of channels assigned to group A and Group B is 1.
Subsequent /DRDY pulses will be produced at rate determined by the fastest ODR (lowest decimation) of either Group A or Group B.
In this example, Decimate-By-32 is the lower of the 2, therefore subsequent /DRDY pulses will be produced every 128 MCLK periods. The digital filter result is not fully settled initially. Thus bit 6 is still set. Group_A digital filter will produce a settled result 8882 MCLKs after releasing /SYNC this time Group A bit 6 will be set to 0. Group_B’s result will not be settled at this time. /DRDY will continue to toggle every 128 MCLKs. A new (settled) Group_A filter output will be available every time /DRDY toggles. Group_B is still not settled.
After 17,014 MCLKs, both Group_A and Group_B will produce a settled result.
128 MCLKs later, Group_A will have a new result, but Group_B will not.
128 MCLKs later, both Group_A and Group_B will have a new result.
The last 2 entries above will repeat indefinitely, with the filter results always being settled.
Now since Group B is running at slower rate then in between settled data the output data will be set to all 0's and the bit 5 (repeated data) in the header will be set. 

Thanks,