I found Front-End Amplifier and RC Filter Design for a Precision SAR Analog-to-Digital Converter an excellent guideline for analog input RC filter design.
However, I would like to ask for some additional explanations in the following part of it:
According to the analysis, considering the mentioned ADC configuration, the Voltage step to be settled is 11.042mV @100kHz.
This value gets higher as BW increases, thus the same calculations would give ~110mV @1MHz and vise versa ~1.1mV @1kHz.
Therefore, why should we have at lower BW (<10kHz) a "constant" and significantly higher voltage step of 100mV to settle?
Such a value would give an equivalent RC bandwidth of ~4MHz, which seems an inessential shift to higher cut-off frequencies, in case the max measurement BW is e.g. 100Hz.
It would be great if anyone in the group had the time to answer shortly the above question or provide some directions to reference articles or bibliography.
Thanks in advance!
