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Unable to read/write registers on AD7091-R4

Category: Hardware
Product Number: AD7091R-4BRUZ
Software Version: N/A

Problem: I am unable to read or write registers on the AD7091-R4 ADC.

Environment: I currently have the part connected to a TSSOP to dip adapter that allows me to connect the ADC to the MCU via a breadboard and jumper wires.  At this stage, I’m simply trying to make sure driver code works for the part before a custom board is built.  As such, this breadboard approach doesn’t include any of the capacitors/resistors that may connected to some of the AD7091-R4 pins.  I wouldn’t think this would influence the SPI capabilities but perhaps this is where the issue lies.  Here is a diagram of my current test setup followed by the intended schematic for the custom board.

Approach 1: Reset via RESET pin + software reset

  1. Reset is done by first setting RESET pin high for 1ms, low for 1ms, then back high. At this stage voltage has already been applied to VDD of the AD7091-R4.
  2. Three SPI transactions take place next, a software reset (0x1600), a write of the configuration register (0x1400), and a read back of the configuration register (0x1000). Each SPI transaction is preceded by pulling the CONVST pin low for ~437ns. This may only be necessary for reading the conversion result register. However, it is here as the timing diagrams in the datasheet show CONVST being pulled low before all SPI transactions.
  3. As shown in the next two captures, the read back value of the configuration register is not 0x1 as programmed in step 2.

Approach 2: Reset via 66 CONVST pulses + software reset

  1. Reset is done by sending 66 CONVST pulses with a pulse width of ~2.563μs. At this stage voltage has already been applied to VDD of the AD7091-R4 and RESET is held high.
  2. Three SPI transactions take place next, a software reset (0x1600), a write of the configuration register (0x1400), and a read back of the configuration register (0x1000). Each SPI transaction is preceded by pulling the CONVST pin low for ~437ns. This may only be necessary for reading the conversion result register but it is here as the timing diagrams in the datasheet show CONVST being pulled low before all SPI transactions.
  3. As shown in the next capture, the read back value of the configuration register is not 0x1 as programmed in step 2.

Approach 3: Reset via 66 CONVST pulses (no software reset and no preceding CONVST pulses)

Same read back results as Approach 1 and 2.

Any help is appreciated.

Thanks,

Mark

  • Hi, 

    I have some questions regarding the issue. Does the ADC converts properly? can you read some measurements from the software? Can you share more about the occurence of timing data in relative to sclk specifically in bit 10? Why is the MISO is constantly high is it connected to somewhere?

    One possible cause of the read/write issue is probably the polarity of sckl. Try using the CPOL=1.

    Regards,

    Andrei 

  • Hi Andrei,

    The ADC does not convert properly either as I'm also unable to program the CHANNEL register.  The SPI peripheral is already configured as CPOL=1 and CPHA =1. The MISO high issue has been resolved by swapping out the SOC adapter that the ADC was sitting on.  However, now it looks like MISO never goes high with any response.  Here is another snap of the tail end of the 66 CONVST reset sequence following by a software reset, configuration register write, and configuration register read.

    Thanks,

    Mark

  • I did see one issue with the 66 reset pulses in that they did not adhere to the timing specification tCNVPW being between 10 and 500ns.  I have fixed that issue here but still see the same result.

  • The issue has been resolved in two forms.
    1. Two decoupling capacitors were added to REGCAP and REGin/REGout.  This fixed the MISO always high issue.

    2. The timing of the register reads was misunderstood on my part.  Note that the register contents shows up in the next register read as per the diagram here: