Unable to read/write registers on AD7091-R4

Problem: I am unable to read or write registers on the AD7091-R4 ADC.

Environment: I currently have the part connected to a TSSOP to dip adapter that allows me to connect the ADC to the MCU via a breadboard and jumper wires.  At this stage, I’m simply trying to make sure driver code works for the part before a custom board is built.  As such, this breadboard approach doesn’t include any of the capacitors/resistors that may connected to some of the AD7091-R4 pins.  I wouldn’t think this would influence the SPI capabilities but perhaps this is where the issue lies.  Here is a diagram of my current test setup followed by the intended schematic for the custom board.

Approach 1: Reset via RESET pin + software reset

1. Reset is done by first setting RESET pin high for 1ms, low for 1ms, then back high. At this stage voltage has already been applied to VDD of the AD7091-R4.
2. Three SPI transactions take place next, a software reset (0x1600), a write of the configuration register (0x1400), and a read back of the configuration register (0x1000). Each SPI transaction is preceded by pulling the CONVST pin low for ~437ns. This may only be necessary for reading the conversion result register. However, it is here as the timing diagrams in the datasheet show CONVST being pulled low before all SPI transactions.
3. As shown in the next two captures, the read back value of the configuration register is not 0x1 as programmed in step 2.

Approach 2: Reset via 66 CONVST pulses + software reset

1. Reset is done by sending 66 CONVST pulses with a pulse width of ~2.563μs. At this stage voltage has already been applied to VDD of the AD7091-R4 and RESET is held high.
2. Three SPI transactions take place next, a software reset (0x1600), a write of the configuration register (0x1400), and a read back of the configuration register (0x1000). Each SPI transaction is preceded by pulling the CONVST pin low for ~437ns. This may only be necessary for reading the conversion result register but it is here as the timing diagrams in the datasheet show CONVST being pulled low before all SPI transactions.
3. As shown in the next capture, the read back value of the configuration register is not 0x1 as programmed in step 2.

Approach 3: Reset via 66 CONVST pulses (no software reset and no preceding CONVST pulses)

Same read back results as Approach 1 and 2.

Any help is appreciated.

Thanks,

Mark